1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for SPEAr320 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "spear3xx.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun ahb { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun compatible = "simple-bus"; 15*4882a593Smuzhiyun ranges = <0x40000000 0x40000000 0x80000000 16*4882a593Smuzhiyun 0xd0000000 0xd0000000 0x30000000>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun pinmux: pinmux@b3000000 { 19*4882a593Smuzhiyun compatible = "st,spear320-pinmux"; 20*4882a593Smuzhiyun reg = <0xb3000000 0x1000>; 21*4882a593Smuzhiyun #gpio-range-cells = <3>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun clcd@90000000 { 25*4882a593Smuzhiyun compatible = "arm,pl110", "arm,primecell"; 26*4882a593Smuzhiyun reg = <0x90000000 0x1000>; 27*4882a593Smuzhiyun interrupts = <8>; 28*4882a593Smuzhiyun interrupt-parent = <&shirq>; 29*4882a593Smuzhiyun status = "disabled"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun fsmc: flash@4c000000 { 33*4882a593Smuzhiyun compatible = "st,spear600-fsmc-nand"; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <1>; 36*4882a593Smuzhiyun reg = <0x4c000000 0x1000 /* FSMC Register */ 37*4882a593Smuzhiyun 0x50000000 0x0010 /* NAND Base DATA */ 38*4882a593Smuzhiyun 0x50020000 0x0010 /* NAND Base ADDR */ 39*4882a593Smuzhiyun 0x50010000 0x0010>; /* NAND Base CMD */ 40*4882a593Smuzhiyun reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 41*4882a593Smuzhiyun status = "disabled"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun sdhci@70000000 { 45*4882a593Smuzhiyun compatible = "st,sdhci-spear"; 46*4882a593Smuzhiyun reg = <0x70000000 0x100>; 47*4882a593Smuzhiyun interrupts = <10>; 48*4882a593Smuzhiyun interrupt-parent = <&shirq>; 49*4882a593Smuzhiyun status = "disabled"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun shirq: interrupt-controller@0xb3000000 { 53*4882a593Smuzhiyun compatible = "st,spear320-shirq"; 54*4882a593Smuzhiyun reg = <0xb3000000 0x1000>; 55*4882a593Smuzhiyun interrupts = <30 28 29 1>; 56*4882a593Smuzhiyun #interrupt-cells = <1>; 57*4882a593Smuzhiyun interrupt-controller; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun spi1: spi@a5000000 { 61*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 62*4882a593Smuzhiyun reg = <0xa5000000 0x1000>; 63*4882a593Smuzhiyun interrupts = <15>; 64*4882a593Smuzhiyun interrupt-parent = <&shirq>; 65*4882a593Smuzhiyun #address-cells = <1>; 66*4882a593Smuzhiyun #size-cells = <0>; 67*4882a593Smuzhiyun status = "disabled"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun spi2: spi@a6000000 { 71*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 72*4882a593Smuzhiyun reg = <0xa6000000 0x1000>; 73*4882a593Smuzhiyun interrupts = <16>; 74*4882a593Smuzhiyun interrupt-parent = <&shirq>; 75*4882a593Smuzhiyun #address-cells = <1>; 76*4882a593Smuzhiyun #size-cells = <0>; 77*4882a593Smuzhiyun status = "disabled"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pwm: pwm@a8000000 { 81*4882a593Smuzhiyun compatible ="st,spear-pwm"; 82*4882a593Smuzhiyun reg = <0xa8000000 0x1000>; 83*4882a593Smuzhiyun #pwm-cells = <2>; 84*4882a593Smuzhiyun status = "disabled"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun apb { 88*4882a593Smuzhiyun #address-cells = <1>; 89*4882a593Smuzhiyun #size-cells = <1>; 90*4882a593Smuzhiyun compatible = "simple-bus"; 91*4882a593Smuzhiyun ranges = <0xa0000000 0xa0000000 0x20000000 92*4882a593Smuzhiyun 0xd0000000 0xd0000000 0x30000000>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun i2c1: i2c@a7000000 { 95*4882a593Smuzhiyun #address-cells = <1>; 96*4882a593Smuzhiyun #size-cells = <0>; 97*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 98*4882a593Smuzhiyun reg = <0xa7000000 0x1000>; 99*4882a593Smuzhiyun interrupts = <21>; 100*4882a593Smuzhiyun interrupt-parent = <&shirq>; 101*4882a593Smuzhiyun status = "disabled"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun serial@a3000000 { 105*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 106*4882a593Smuzhiyun reg = <0xa3000000 0x1000>; 107*4882a593Smuzhiyun interrupts = <13>; 108*4882a593Smuzhiyun interrupt-parent = <&shirq>; 109*4882a593Smuzhiyun status = "disabled"; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun serial@a4000000 { 113*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 114*4882a593Smuzhiyun reg = <0xa4000000 0x1000>; 115*4882a593Smuzhiyun interrupts = <14>; 116*4882a593Smuzhiyun interrupt-parent = <&shirq>; 117*4882a593Smuzhiyun status = "disabled"; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun gpiopinctrl: gpio@b3000000 { 121*4882a593Smuzhiyun compatible = "st,spear-plgpio"; 122*4882a593Smuzhiyun reg = <0xb3000000 0x1000>; 123*4882a593Smuzhiyun #interrupt-cells = <1>; 124*4882a593Smuzhiyun interrupt-controller; 125*4882a593Smuzhiyun gpio-controller; 126*4882a593Smuzhiyun #gpio-cells = <2>; 127*4882a593Smuzhiyun gpio-ranges = <&pinmux 0 0 102>; 128*4882a593Smuzhiyun status = "disabled"; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun st-plgpio,ngpio = <102>; 131*4882a593Smuzhiyun st-plgpio,enb-reg = <0x24>; 132*4882a593Smuzhiyun st-plgpio,wdata-reg = <0x34>; 133*4882a593Smuzhiyun st-plgpio,dir-reg = <0x44>; 134*4882a593Smuzhiyun st-plgpio,ie-reg = <0x64>; 135*4882a593Smuzhiyun st-plgpio,rdata-reg = <0x54>; 136*4882a593Smuzhiyun st-plgpio,mis-reg = <0x84>; 137*4882a593Smuzhiyun st-plgpio,eit-reg = <0x94>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun}; 142