Lines Matching +full:0 +full:xd0000000

49  * internal registers to 0xf1000000 (instead of the default
50  * 0xd0000000). The 0xf1000000 is the default used by the recent,
53  * left internal registers mapped at 0xd0000000. If you are in this
78 		reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
82 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
83 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
84 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
110 				phy0: ethernet-phy@0 {
111 					reg = <0>;
133 				spi-flash@0 {
138 					reg = <0>; /* Chip select 0 */