xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/designware-pcie.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Synopsys DesignWare PCIe interface
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun- compatible:
5*4882a593Smuzhiyun	"snps,dw-pcie" for RC mode;
6*4882a593Smuzhiyun	"snps,dw-pcie-ep" for EP mode;
7*4882a593Smuzhiyun- reg: For designware cores version < 4.80 contains the configuration
8*4882a593Smuzhiyun       address space. For designware core version >= 4.80, contains
9*4882a593Smuzhiyun       the configuration and ATU address space
10*4882a593Smuzhiyun- reg-names: Must be "config" for the PCIe configuration space and "atu" for
11*4882a593Smuzhiyun	     the ATU address space.
12*4882a593Smuzhiyun    (The old way of getting the configuration address space from "ranges"
13*4882a593Smuzhiyun    is deprecated and should be avoided.)
14*4882a593SmuzhiyunRC mode:
15*4882a593Smuzhiyun- #address-cells: set to <3>
16*4882a593Smuzhiyun- #size-cells: set to <2>
17*4882a593Smuzhiyun- device_type: set to "pci"
18*4882a593Smuzhiyun- ranges: ranges for the PCI memory and I/O regions
19*4882a593Smuzhiyun- #interrupt-cells: set to <1>
20*4882a593Smuzhiyun- interrupt-map-mask and interrupt-map: standard PCI
21*4882a593Smuzhiyun	properties to define the mapping of the PCIe interface to interrupt
22*4882a593Smuzhiyun	numbers.
23*4882a593SmuzhiyunEP mode:
24*4882a593Smuzhiyun- num-ib-windows: number of inbound address translation windows
25*4882a593Smuzhiyun- num-ob-windows: number of outbound address translation windows
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunOptional properties:
28*4882a593Smuzhiyun- num-lanes: number of lanes to use (this property should be specified unless
29*4882a593Smuzhiyun  the link is brought already up in BIOS)
30*4882a593Smuzhiyun- reset-gpio: GPIO pin number of power good signal
31*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names.
32*4882a593Smuzhiyun	See ../clocks/clock-bindings.txt for details.
33*4882a593Smuzhiyun- clock-names: Must include the following entries:
34*4882a593Smuzhiyun	- "pcie"
35*4882a593Smuzhiyun	- "pcie_bus"
36*4882a593Smuzhiyun- snps,enable-cdm-check: This is a boolean property and if present enables
37*4882a593Smuzhiyun   automatic checking of CDM (Configuration Dependent Module) registers
38*4882a593Smuzhiyun   for data corruption. CDM registers include standard PCIe configuration
39*4882a593Smuzhiyun   space registers, Port Logic registers, DMA and iATU (internal Address
40*4882a593Smuzhiyun   Translation Unit) registers.
41*4882a593SmuzhiyunRC mode:
42*4882a593Smuzhiyun- num-viewport: number of view ports configured in hardware. If a platform
43*4882a593Smuzhiyun  does not specify it, the driver assumes 2.
44*4882a593Smuzhiyun- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
45*4882a593Smuzhiyun  to specify this property, to keep backwards compatibility a range of
46*4882a593Smuzhiyun  0x00-0xff is assumed if not present)
47*4882a593Smuzhiyun
48*4882a593SmuzhiyunEP mode:
49*4882a593Smuzhiyun- max-functions: maximum number of functions that can be configured
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunExample configuration:
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	pcie: pcie@dfc00000 {
54*4882a593Smuzhiyun		compatible = "snps,dw-pcie";
55*4882a593Smuzhiyun		reg = <0xdfc00000 0x0001000>, /* IP registers */
56*4882a593Smuzhiyun		      <0xd0000000 0x0002000>; /* Configuration space */
57*4882a593Smuzhiyun		reg-names = "dbi", "config";
58*4882a593Smuzhiyun		#address-cells = <3>;
59*4882a593Smuzhiyun		#size-cells = <2>;
60*4882a593Smuzhiyun		device_type = "pci";
61*4882a593Smuzhiyun		ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
62*4882a593Smuzhiyun			  0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
63*4882a593Smuzhiyun		interrupts = <25>, <24>;
64*4882a593Smuzhiyun		#interrupt-cells = <1>;
65*4882a593Smuzhiyun		num-lanes = <1>;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyunor
68*4882a593Smuzhiyun	pcie: pcie@dfc00000 {
69*4882a593Smuzhiyun		compatible = "snps,dw-pcie-ep";
70*4882a593Smuzhiyun		reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
71*4882a593Smuzhiyun		      <0xdfc01000 0x0001000>, /* IP registers 2 */
72*4882a593Smuzhiyun		      <0xd0000000 0x2000000>; /* Configuration space */
73*4882a593Smuzhiyun		reg-names = "dbi", "dbi2", "addr_space";
74*4882a593Smuzhiyun		num-ib-windows = <6>;
75*4882a593Smuzhiyun		num-ob-windows = <2>;
76*4882a593Smuzhiyun		num-lanes = <1>;
77*4882a593Smuzhiyun	};
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