1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/interrupt-router/intel-irq.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/* ICH9 IRQ router has discrete PIRQ control registers */ 12*4882a593Smuzhiyun#undef PIRQE 13*4882a593Smuzhiyun#undef PIRQF 14*4882a593Smuzhiyun#undef PIRQG 15*4882a593Smuzhiyun#undef PIRQH 16*4882a593Smuzhiyun#define PIRQE 8 17*4882a593Smuzhiyun#define PIRQF 9 18*4882a593Smuzhiyun#define PIRQG 10 19*4882a593Smuzhiyun#define PIRQH 11 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/include/ "skeleton.dtsi" 22*4882a593Smuzhiyun/include/ "serial.dtsi" 23*4882a593Smuzhiyun/include/ "keyboard.dtsi" 24*4882a593Smuzhiyun/include/ "rtc.dtsi" 25*4882a593Smuzhiyun/include/ "tsc_timer.dtsi" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/ { 28*4882a593Smuzhiyun model = "QEMU x86 (Q35)"; 29*4882a593Smuzhiyun compatible = "qemu,x86"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun config { 32*4882a593Smuzhiyun silent_console = <0>; 33*4882a593Smuzhiyun u-boot,no-apm-finalize; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun chosen { 37*4882a593Smuzhiyun stdout-path = "/serial"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cpus { 41*4882a593Smuzhiyun #address-cells = <1>; 42*4882a593Smuzhiyun #size-cells = <0>; 43*4882a593Smuzhiyun u-boot,dm-pre-reloc; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun cpu@0 { 46*4882a593Smuzhiyun device_type = "cpu"; 47*4882a593Smuzhiyun compatible = "cpu-qemu"; 48*4882a593Smuzhiyun u-boot,dm-pre-reloc; 49*4882a593Smuzhiyun reg = <0>; 50*4882a593Smuzhiyun intel,apic-id = <0>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun tsc-timer { 55*4882a593Smuzhiyun clock-frequency = <1000000000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun pci { 59*4882a593Smuzhiyun compatible = "pci-x86"; 60*4882a593Smuzhiyun #address-cells = <3>; 61*4882a593Smuzhiyun #size-cells = <2>; 62*4882a593Smuzhiyun u-boot,dm-pre-reloc; 63*4882a593Smuzhiyun ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 64*4882a593Smuzhiyun 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 65*4882a593Smuzhiyun 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun pch@1f,0 { 68*4882a593Smuzhiyun reg = <0x0000f800 0 0 0 0>; 69*4882a593Smuzhiyun compatible = "intel,pch9"; 70*4882a593Smuzhiyun u-boot,dm-pre-reloc; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun irq-router { 73*4882a593Smuzhiyun compatible = "intel,irq-router"; 74*4882a593Smuzhiyun u-boot,dm-pre-reloc; 75*4882a593Smuzhiyun intel,pirq-config = "pci"; 76*4882a593Smuzhiyun intel,actl-8bit; 77*4882a593Smuzhiyun intel,actl-addr = <0x44>; 78*4882a593Smuzhiyun intel,pirq-link = <0x60 8>; 79*4882a593Smuzhiyun intel,pirq-mask = <0x0e40>; 80*4882a593Smuzhiyun intel,pirq-routing = < 81*4882a593Smuzhiyun /* e1000 NIC */ 82*4882a593Smuzhiyun PCI_BDF(0, 2, 0) INTA PIRQG 83*4882a593Smuzhiyun /* ICH9 UHCI */ 84*4882a593Smuzhiyun PCI_BDF(0, 29, 0) INTA PIRQA 85*4882a593Smuzhiyun PCI_BDF(0, 29, 1) INTB PIRQB 86*4882a593Smuzhiyun PCI_BDF(0, 29, 2) INTC PIRQC 87*4882a593Smuzhiyun /* ICH9 EHCI */ 88*4882a593Smuzhiyun PCI_BDF(0, 29, 7) INTD PIRQD 89*4882a593Smuzhiyun /* ICH9 SATA */ 90*4882a593Smuzhiyun PCI_BDF(0, 31, 2) INTA PIRQA 91*4882a593Smuzhiyun >; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun}; 97