xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/armada-xp-db-dxbc2.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree file for DB-DXBC2 board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Allied Telesis Labs
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on armada-xp-db.dts
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Note: this Device Tree assumes that the bootloader has remapped the
10*4882a593Smuzhiyun * internal registers to 0xf1000000 (instead of the default
11*4882a593Smuzhiyun * 0xd0000000). The 0xf1000000 is the default used by the recent,
12*4882a593Smuzhiyun * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
13*4882a593Smuzhiyun * boards were delivered with an older version of the bootloader that
14*4882a593Smuzhiyun * left internal registers mapped at 0xd0000000. If you are in this
15*4882a593Smuzhiyun * situation, you should either update your bootloader (preferred
16*4882a593Smuzhiyun * solution) or the below Device Tree should be adjusted.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/dts-v1/;
20*4882a593Smuzhiyun#include "armada-xp-98dx4251.dtsi"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun/ {
23*4882a593Smuzhiyun	model = "Marvell Bobcat2 Evaluation Board";
24*4882a593Smuzhiyun	compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	chosen {
27*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200 earlyprintk";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	memory {
31*4882a593Smuzhiyun		device_type = "memory";
32*4882a593Smuzhiyun		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun&devbus_bootcs {
38*4882a593Smuzhiyun	status = "okay";
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	/* Device Bus parameters are required */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	/* Read parameters */
43*4882a593Smuzhiyun	devbus,bus-width    = <16>;
44*4882a593Smuzhiyun	devbus,turn-off-ps  = <60000>;
45*4882a593Smuzhiyun	devbus,badr-skew-ps = <0>;
46*4882a593Smuzhiyun	devbus,acc-first-ps = <124000>;
47*4882a593Smuzhiyun	devbus,acc-next-ps  = <248000>;
48*4882a593Smuzhiyun	devbus,rd-setup-ps  = <0>;
49*4882a593Smuzhiyun	devbus,rd-hold-ps   = <0>;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	/* Write parameters */
52*4882a593Smuzhiyun	devbus,sync-enable = <0>;
53*4882a593Smuzhiyun	devbus,wr-high-ps  = <60000>;
54*4882a593Smuzhiyun	devbus,wr-low-ps   = <60000>;
55*4882a593Smuzhiyun	devbus,ale-wr-ps   = <60000>;
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&i2c0 {
59*4882a593Smuzhiyun	clock-frequency = <100000>;
60*4882a593Smuzhiyun	status = "okay";
61*4882a593Smuzhiyun};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun&uart0 {
64*4882a593Smuzhiyun	status = "okay";
65*4882a593Smuzhiyun};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun&uart1 {
68*4882a593Smuzhiyun	status = "okay";
69*4882a593Smuzhiyun};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun&nand_controller {
72*4882a593Smuzhiyun	status = "okay";
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun	nand@0 {
75*4882a593Smuzhiyun		reg = <0>;
76*4882a593Smuzhiyun		label = "pxa3xx_nand-0";
77*4882a593Smuzhiyun		nand-rb = <0>;
78*4882a593Smuzhiyun		marvell,nand-keep-config;
79*4882a593Smuzhiyun		nand-on-flash-bbt;
80*4882a593Smuzhiyun		nand-ecc-strength = <4>;
81*4882a593Smuzhiyun		nand-ecc-step-size = <512>;
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun&sdio {
86*4882a593Smuzhiyun	pinctrl-0 = <&sdio_pins>;
87*4882a593Smuzhiyun	pinctrl-names = "default";
88*4882a593Smuzhiyun	status = "okay";
89*4882a593Smuzhiyun	/* No CD or WP GPIOs */
90*4882a593Smuzhiyun	broken-cd;
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&spi0 {
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	spi-flash@0 {
97*4882a593Smuzhiyun		#address-cells = <1>;
98*4882a593Smuzhiyun		#size-cells = <1>;
99*4882a593Smuzhiyun		compatible = "m25p64";
100*4882a593Smuzhiyun		reg = <0>; /* Chip select 0 */
101*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
102*4882a593Smuzhiyun		m25p,fast-read;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		partition@u-boot {
105*4882a593Smuzhiyun			reg = <0x00000000 0x00100000>;
106*4882a593Smuzhiyun			label = "u-boot";
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun		partition@u-boot-env {
109*4882a593Smuzhiyun			reg = <0x00100000 0x00040000>;
110*4882a593Smuzhiyun			label = "u-boot-env";
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun		partition@unused {
113*4882a593Smuzhiyun			reg = <0x00140000 0x00ec0000>;
114*4882a593Smuzhiyun			label = "unused";
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun};
119