1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR MIT 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2014 Carlo Caione <carlo@caione.org> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "meson.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Amlogic Meson6 SoC"; 10*4882a593Smuzhiyun compatible = "amlogic,meson6"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun cpus { 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <0>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun cpu@200 { 17*4882a593Smuzhiyun device_type = "cpu"; 18*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 19*4882a593Smuzhiyun next-level-cache = <&L2>; 20*4882a593Smuzhiyun reg = <0x200>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cpu@201 { 24*4882a593Smuzhiyun device_type = "cpu"; 25*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 26*4882a593Smuzhiyun next-level-cache = <&L2>; 27*4882a593Smuzhiyun reg = <0x201>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun apb2: bus@d0000000 { 32*4882a593Smuzhiyun compatible = "simple-bus"; 33*4882a593Smuzhiyun reg = <0xd0000000 0x40000>; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <1>; 36*4882a593Smuzhiyun ranges = <0x0 0xd0000000 0x40000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clk81: clk@0 { 40*4882a593Smuzhiyun #clock-cells = <0>; 41*4882a593Smuzhiyun compatible = "fixed-clock"; 42*4882a593Smuzhiyun clock-frequency = <200000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; /* end of / */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&efuse { 47*4882a593Smuzhiyun status = "disabled"; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&timer_abcde { 51*4882a593Smuzhiyun clocks = <&xtal>, <&clk81>; 52*4882a593Smuzhiyun clock-names = "xtal", "pclk"; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&uart_AO { 56*4882a593Smuzhiyun clocks = <&xtal>, <&clk81>, <&clk81>; 57*4882a593Smuzhiyun clock-names = "xtal", "pclk", "baud"; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&uart_A { 61*4882a593Smuzhiyun clocks = <&xtal>, <&clk81>, <&clk81>; 62*4882a593Smuzhiyun clock-names = "xtal", "pclk", "baud"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&uart_B { 66*4882a593Smuzhiyun clocks = <&xtal>, <&clk81>, <&clk81>; 67*4882a593Smuzhiyun clock-names = "xtal", "pclk", "baud"; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&uart_C { 71*4882a593Smuzhiyun clocks = <&xtal>, <&clk81>, <&clk81>; 72*4882a593Smuzhiyun clock-names = "xtal", "pclk", "baud"; 73*4882a593Smuzhiyun}; 74