1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Synology DS213j 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Note: this Device Tree assumes that the bootloader has remapped the 8*4882a593Smuzhiyun * internal registers to 0xf1000000 (instead of the old 0xd0000000). 9*4882a593Smuzhiyun * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot 10*4882a593Smuzhiyun * bootloaders provided by Marvell. It is used in recent versions of 11*4882a593Smuzhiyun * DSM software provided by Synology. Nonetheless, some earlier boards 12*4882a593Smuzhiyun * were delivered with an older version of u-boot that left internal 13*4882a593Smuzhiyun * registers mapped at 0xd0000000. If you have such a device you will 14*4882a593Smuzhiyun * not be able to directly boot a kernel based on this Device Tree. In 15*4882a593Smuzhiyun * that case, the preferred solution is to update your bootloader (e.g. 16*4882a593Smuzhiyun * by upgrading to latest version of DSM, or building a new one and 17*4882a593Smuzhiyun * installing it from u-boot prompt) or adjust the Devive Tree 18*4882a593Smuzhiyun * (s/0xf1000000/0xd0000000/ in 'ranges' below). 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/dts-v1/; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 24*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 25*4882a593Smuzhiyun#include "armada-370.dtsi" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/ { 28*4882a593Smuzhiyun model = "Synology DS213j"; 29*4882a593Smuzhiyun compatible = "synology,ds213j", "marvell,armada370", 30*4882a593Smuzhiyun "marvell,armada-370-xp"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun chosen { 33*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun memory@0 { 37*4882a593Smuzhiyun device_type = "memory"; 38*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; /* 512 MB */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun soc { 42*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 43*4882a593Smuzhiyun MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 44*4882a593Smuzhiyun MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun internal-regs { 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* RTC provided by Seiko S-35390A I2C RTC chip below */ 49*4882a593Smuzhiyun rtc@10300 { 50*4882a593Smuzhiyun status = "disabled"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun i2c@11000 { 54*4882a593Smuzhiyun compatible = "marvell,mv64xxx-i2c"; 55*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun clock-frequency = <400000>; 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Main device RTC chip */ 61*4882a593Smuzhiyun s35390a: s35390a@30 { 62*4882a593Smuzhiyun compatible = "sii,s35390a"; 63*4882a593Smuzhiyun reg = <0x30>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Connected to a header on device's PCB */ 68*4882a593Smuzhiyun serial@12000 { 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Connected to a TI MSP430F2111 for power control */ 73*4882a593Smuzhiyun serial@12100 { 74*4882a593Smuzhiyun status = "okay"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun poweroff@12100 { 78*4882a593Smuzhiyun compatible = "synology,power-off"; 79*4882a593Smuzhiyun reg = <0x12100 0x100>; 80*4882a593Smuzhiyun clocks = <&coreclk 0>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* rear USB port, near reset button */ 84*4882a593Smuzhiyun usb@50000 { 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* rear USB port, near RJ45 port */ 89*4882a593Smuzhiyun usb@51000 { 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun ethernet@70000 { 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun phy = <&phy1>; 96*4882a593Smuzhiyun phy-mode = "sgmii"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun sata@a0000 { 100*4882a593Smuzhiyun nr-ports = <2>; 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun gpio-fan-32-38 { 107*4882a593Smuzhiyun status = "okay"; 108*4882a593Smuzhiyun compatible = "gpio-fan"; 109*4882a593Smuzhiyun pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin 110*4882a593Smuzhiyun &fan_ctrl_high_pin &fan_alarm_pin>; 111*4882a593Smuzhiyun pinctrl-names = "default"; 112*4882a593Smuzhiyun gpios = <&gpio1 31 GPIO_ACTIVE_HIGH 113*4882a593Smuzhiyun &gpio2 0 GPIO_ACTIVE_HIGH 114*4882a593Smuzhiyun &gpio2 1 GPIO_ACTIVE_HIGH>; 115*4882a593Smuzhiyun alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 116*4882a593Smuzhiyun gpio-fan,speed-map = < 0 0 117*4882a593Smuzhiyun 1000 1 118*4882a593Smuzhiyun 1150 2 119*4882a593Smuzhiyun 1350 4 120*4882a593Smuzhiyun 1500 3 121*4882a593Smuzhiyun 1650 5 122*4882a593Smuzhiyun 1750 6 123*4882a593Smuzhiyun 1900 7 >; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun gpio-leds { 127*4882a593Smuzhiyun compatible = "gpio-leds"; 128*4882a593Smuzhiyun pinctrl-0 = <&disk1_led_pin 129*4882a593Smuzhiyun &disk2_led_pin>; 130*4882a593Smuzhiyun pinctrl-names = "default"; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun disk1-led-amber { 133*4882a593Smuzhiyun label = "synology:amber:disk1"; 134*4882a593Smuzhiyun gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; 135*4882a593Smuzhiyun default-state = "keep"; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun disk2-led-amber { 139*4882a593Smuzhiyun label = "synology:amber:disk2"; 140*4882a593Smuzhiyun gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 141*4882a593Smuzhiyun default-state = "keep"; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun regulators { 146*4882a593Smuzhiyun compatible = "simple-bus"; 147*4882a593Smuzhiyun #address-cells = <1>; 148*4882a593Smuzhiyun #size-cells = <0>; 149*4882a593Smuzhiyun pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; 150*4882a593Smuzhiyun pinctrl-names = "default"; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun sata1_regulator: sata1-regulator@1 { 153*4882a593Smuzhiyun compatible = "regulator-fixed"; 154*4882a593Smuzhiyun reg = <1>; 155*4882a593Smuzhiyun regulator-name = "SATA1 Power"; 156*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 157*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 158*4882a593Smuzhiyun startup-delay-us = <2000000>; 159*4882a593Smuzhiyun enable-active-high; 160*4882a593Smuzhiyun regulator-always-on; 161*4882a593Smuzhiyun regulator-boot-on; 162*4882a593Smuzhiyun gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun sata2_regulator: sata2-regulator@2 { 166*4882a593Smuzhiyun compatible = "regulator-fixed"; 167*4882a593Smuzhiyun reg = <2>; 168*4882a593Smuzhiyun regulator-name = "SATA2 Power"; 169*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 170*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 171*4882a593Smuzhiyun startup-delay-us = <4000000>; 172*4882a593Smuzhiyun enable-active-high; 173*4882a593Smuzhiyun regulator-always-on; 174*4882a593Smuzhiyun regulator-boot-on; 175*4882a593Smuzhiyun gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun&mdio { 181*4882a593Smuzhiyun phy1: ethernet-phy@1 { /* Marvell 88E1512 */ 182*4882a593Smuzhiyun reg = <1>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&pinctrl { 187*4882a593Smuzhiyun disk1_led_pin: disk1-led-pin { 188*4882a593Smuzhiyun marvell,pins = "mpp31"; 189*4882a593Smuzhiyun marvell,function = "gpio"; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun disk2_led_pin: disk2-led-pin { 193*4882a593Smuzhiyun marvell,pins = "mpp32"; 194*4882a593Smuzhiyun marvell,function = "gpio"; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun sata1_pwr_pin: sata1-pwr-pin { 198*4882a593Smuzhiyun marvell,pins = "mpp37"; 199*4882a593Smuzhiyun marvell,function = "gpio"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun sata2_pwr_pin: sata2-pwr-pin { 203*4882a593Smuzhiyun marvell,pins = "mpp62"; 204*4882a593Smuzhiyun marvell,function = "gpio"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun sata1_pres_pin: sata1-pres-pin { 208*4882a593Smuzhiyun marvell,pins = "mpp60"; 209*4882a593Smuzhiyun marvell,function = "gpio"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun sata2_pres_pin: sata2-pres-pin { 213*4882a593Smuzhiyun marvell,pins = "mpp48"; 214*4882a593Smuzhiyun marvell,function = "gpio"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun syno_id_bit0_pin: syno-id-bit0-pin { 218*4882a593Smuzhiyun marvell,pins = "mpp55"; 219*4882a593Smuzhiyun marvell,function = "gpio"; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun syno_id_bit1_pin: syno-id-bit1-pin { 223*4882a593Smuzhiyun marvell,pins = "mpp56"; 224*4882a593Smuzhiyun marvell,function = "gpio"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun syno_id_bit2_pin: syno-id-bit2-pin { 228*4882a593Smuzhiyun marvell,pins = "mpp57"; 229*4882a593Smuzhiyun marvell,function = "gpio"; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun syno_id_bit3_pin: syno-id-bit3-pin { 233*4882a593Smuzhiyun marvell,pins = "mpp58"; 234*4882a593Smuzhiyun marvell,function = "gpio"; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun fan_ctrl_low_pin: fan-ctrl-low-pin { 238*4882a593Smuzhiyun marvell,pins = "mpp65"; 239*4882a593Smuzhiyun marvell,function = "gpio"; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun fan_ctrl_mid_pin: fan-ctrl-mid-pin { 243*4882a593Smuzhiyun marvell,pins = "mpp64"; 244*4882a593Smuzhiyun marvell,function = "gpio"; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun fan_ctrl_high_pin: fan-ctrl-high-pin { 248*4882a593Smuzhiyun marvell,pins = "mpp63"; 249*4882a593Smuzhiyun marvell,function = "gpio"; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun fan_alarm_pin: fan-alarm-pin { 253*4882a593Smuzhiyun marvell,pins = "mpp38"; 254*4882a593Smuzhiyun marvell,function = "gpio"; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&spi0 { 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun spi-flash@0 { 262*4882a593Smuzhiyun #address-cells = <1>; 263*4882a593Smuzhiyun #size-cells = <1>; 264*4882a593Smuzhiyun compatible = "micron,n25q064", "jedec,spi-nor"; 265*4882a593Smuzhiyun reg = <0>; /* Chip select 0 */ 266*4882a593Smuzhiyun spi-max-frequency = <20000000>; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* 269*4882a593Smuzhiyun * Warning! 270*4882a593Smuzhiyun * 271*4882a593Smuzhiyun * Synology u-boot uses its compiled-in environment 272*4882a593Smuzhiyun * and it seems Synology did not care to change u-boot 273*4882a593Smuzhiyun * default configuration in order to allow saving a 274*4882a593Smuzhiyun * modified environment at a sensible location. So, 275*4882a593Smuzhiyun * if you do a 'saveenv' under u-boot, your modified 276*4882a593Smuzhiyun * environment will be saved at 1MB after the start 277*4882a593Smuzhiyun * of the flash, i.e. in the middle of the uImage. 278*4882a593Smuzhiyun * For that reason, it is strongly advised not to 279*4882a593Smuzhiyun * change the default environment, unless you know 280*4882a593Smuzhiyun * what you are doing. 281*4882a593Smuzhiyun */ 282*4882a593Smuzhiyun partition@0 { /* u-boot */ 283*4882a593Smuzhiyun label = "RedBoot"; 284*4882a593Smuzhiyun reg = <0x00000000 0x000c0000>; /* 768KB */ 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun partition@c0000 { /* uImage */ 288*4882a593Smuzhiyun label = "zImage"; 289*4882a593Smuzhiyun reg = <0x000c0000 0x002d0000>; /* 2880KB */ 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun partition@390000 { /* uInitramfs */ 293*4882a593Smuzhiyun label = "rd.gz"; 294*4882a593Smuzhiyun reg = <0x00390000 0x00440000>; /* 4250KB */ 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun partition@7d0000 { /* MAC address and serial number */ 298*4882a593Smuzhiyun label = "vendor"; 299*4882a593Smuzhiyun reg = <0x007d0000 0x00010000>; /* 64KB */ 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun partition@7e0000 { 303*4882a593Smuzhiyun label = "RedBoot config"; 304*4882a593Smuzhiyun reg = <0x007e0000 0x00010000>; /* 64KB */ 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun partition@7f0000 { 308*4882a593Smuzhiyun label = "FIS directory"; 309*4882a593Smuzhiyun reg = <0x007f0000 0x00010000>; /* 64KB */ 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun}; 313