common: Add smp boot support

smp.S from u-boot-tb: #248761 (rk3576: mos: smp.c for dual boot device)

Change-Id: I0f82619f51696b6460f12fcf7912a4a1bfd05746
Signed-off-by: Joseph Chen <chenjh@rock-chi

common: Add smp boot support

smp.S from u-boot-tb: #248761 (rk3576: mos: smp.c for dual boot device)

Change-Id: I0f82619f51696b6460f12fcf7912a4a1bfd05746
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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arm: v8: Introduce spinlock support

Change-Id: Ib47aafb5695470464e5d5f176ad35382d19d1bdd
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

arch: arm: Add ARM_ERRATA_814220

Sync from kernel.

- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.

- Implications:
Code that intends to clean dirty data from L1

arch: arm: Add ARM_ERRATA_814220

Sync from kernel.

- ERRATA_814220:
Cache maintenance by set/way operations can execute out of order.

- Implications:
Code that intends to clean dirty data from L1 to L2 and then from L2 to L3 using
set/way operations might not behave as expected. The L2 to L3 operation might
happen first and result in dirty data remaining in L2 after the L1 to L2 operation
has completed.
If dirty data remains in L2 then an external agent, such as a DMA agent, might
observe stale data.
If the processor is reset or powered-down while dirty data remains in L2 then
the dirty data will be lost.

- Workaround:
Correct ordering between set/way cache maintenance operations can be forced by
executing a DSB before changing cache levels.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide0a03b891cfa471f7cee2033430a02f2c5ec59b

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rockchip: Add arch timer 1Ghz support

Change-Id: I8e58b15be1823e732852a2aa76cc98813e6b4fe9
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

armv8: fwcall: Fix potential compile error

"arch/arm/cpu/armv8/fwcall.c:136: multiple definition of `reset_misc'"

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If8cebccdf22d33868835

armv8: fwcall: Fix potential compile error

"arch/arm/cpu/armv8/fwcall.c:136: multiple definition of `reset_misc'"

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If8cebccdf22d3386883556b1d6666104b33f0ab7

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arm: v8: Add SPL option for ARMV8 CE

Providing option for rk3588 and rk3568 to disable SPL ARMV8 CE.
Cortex-a55 need platform specific initial before use SPL ARMV8 CE.

Signed-off-by: Joseph Chen <c

arm: v8: Add SPL option for ARMV8 CE

Providing option for rk3588 and rk3568 to disable SPL ARMV8 CE.
Cortex-a55 need platform specific initial before use SPL ARMV8 CE.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I229b51d62f7102f8df2aa209ae1b7a666e0af25d

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cpu: armv7: Add udelay support for 32-bits platforms in board_init_f()

Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: I949e738d230dfc5f84421422f7d0201b66ff31f8

common: Add MP boot support

mp_boot build from: a5185c920.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8f8b2fe45ee87ad0a60e1dfd6f0950f052d4f1e7

UPSTREAM: armv8 SHA-256 using ARMv8 Crypto Extensions

This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs
that have support for the SHA-256 part of the ARM v8 Crypto Extensions.

UPSTREAM: armv8 SHA-256 using ARMv8 Crypto Extensions

This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs
that have support for the SHA-256 part of the ARM v8 Crypto Extensions.

It greatly improves sha-256 based operations, about 17x faster on iMX8M
evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification.

asm implementation is a simplified version of the Linux version (from
Ard Biesheuvel).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I653b755a29f2cb4e3c1290b02ad48de9d413b455
(cherry picked from commit 0fcc1c76d1acaa68a0675f0baa0e5d9a25908bae)

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UPSTREAM: armv8 SHA-1 using ARMv8 Crypto Extensions:

This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs
that have support for the SHA-1 part of the ARM v8 Crypto Extensions.

It gr

UPSTREAM: armv8 SHA-1 using ARMv8 Crypto Extensions:

This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs
that have support for the SHA-1 part of the ARM v8 Crypto Extensions.

It greatly improves sha-1 based operations, about 10x faster on iMX8M
evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification.

asm implementation is a simplified version of the Linux version (from
Ard Biesheuvel).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If03c03aafeba7a366b9b3fadce27b43f99d78e85
(cherry picked from commit 084d8e6bf9ea6673e94f798c5c3793893eb783ab)

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arm: v8: Move cpu init from crt0_64.S to start.S

Do init before secondary cpu jump.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idd247743048907384d7f1ed13abf42403ae813d7

cpu: armv7: Disable align access in cpu_init_cp15()

There is unalign access when decompress firmware.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I780e4a0c3bd0a5285f5624e79bdc7184

cpu: armv7: Disable align access in cpu_init_cp15()

There is unalign access when decompress firmware.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I780e4a0c3bd0a5285f5624e79bdc7184c8bbe40f

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arm: cache v8: Add isb sync before __asm_flush_dcache_range() out

Promising flush operation is really done before a DMA start. The
issue was found on eMMC read with RK3588 A76 big core boot.

The sa

arm: cache v8: Add isb sync before __asm_flush_dcache_range() out

Promising flush operation is really done before a DMA start. The
issue was found on eMMC read with RK3588 A76 big core boot.

The same reason as commit:
(1d85e75e20 arm: cache v8: add isb sync for clean/invalidate)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide34f474f8d49f04869cb832a4b382b3c4b31fff

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arm: v7: Add zero CNTVOFF support

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I844ea7592e1448d7e5408b6ec1b26ed80af53358

arm: cache v8: add isb sync for clean/invalidate

When rk3588 boot with big core on U-Boot and enter rockusb
download mode, it works abnormally.

We find that a isb() is neccessary before cache inval

arm: cache v8: add isb sync for clean/invalidate

When rk3588 boot with big core on U-Boot and enter rockusb
download mode, it works abnormally.

We find that a isb() is neccessary before cache invalidate.
We guess that the A76's prefetch performance is too powerful.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I4492a073f4d38b337f177d3d3970ec2c9107d5df

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arm: v7: u-boot.lds: promise 8 byte align

When AArch64 bl31 uses u-boot.dtb passed from SPL, it requires
this fdt in a 8-byte aligned address, otherwise it causes a
unaligned access exception.

If t

arm: v7: u-boot.lds: promise 8 byte align

When AArch64 bl31 uses u-boot.dtb passed from SPL, it requires
this fdt in a 8-byte aligned address, otherwise it causes a
unaligned access exception.

If the u-boot is built with AArch32 mode, it's size maybe
not 8-byte aligned, so does the fdt address.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Icb6797336122f23ef5e82aec731faceb3f54242d

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arm: v8: support disable Dcache

Fix compile error.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6261ccbb89cdfd2e4a81a3ed09fdb4fd71e03ff0

irq: simplify the #if expression

Use CONFIG_IS_ENABLED() is better.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4f514cc1dfb9e0f52521954158172bba1eb8f85

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene ===
When access a illegal address, It results in:
- read: Synchronous data-abort
- write: SError(64-bit)/Asynchronous external abort(32-bit)

=== 64-bit ===
EL3 SError ASynchronous exception in TPL/SPL was already
enabled in start.S and crt0_64.S which sets SCR_EL3.EA=1
and DAIF.A=0. We can test result of TPL/SPL by access address
0xfe108000 in rk3568.
Let's enable SError in U-Boot proper.

=== 32-bit ===
Let's set CPSR.A=0 to enable Asynchronous external abort, we can
test result by access address 0xfe808000 in rv1126.
Note: TPL/SPL vectors only provides "b ." for all exception entry.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id9f660a9275f69fdc8443ad239aabf79682d95d0

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armv8: sleep.S: fix compile error

LD u-boot
arch/arm/cpu/armv8/built-in.o: In function `cpu_suspend':
arch/arm/cpu/armv8/sleep.S:52:(.text+0x588): relocation truncated to fit: R_AARCH64_ADR_P

armv8: sleep.S: fix compile error

LD u-boot
arch/arm/cpu/armv8/built-in.o: In function `cpu_suspend':
arch/arm/cpu/armv8/sleep.S:52:(.text+0x588): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against `.data'
arch/arm/cpu/armv8/built-in.o: In function `cpu_resume':
arch/arm/cpu/armv8/sleep.S:137:(.text+0x654): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against `.data'
Makefile:1281: recipe for target 'u-boot' failed
make: *** [u-boot] Error 1

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I19cfbe721ff0482eda66c74aa36e1c28d37da93c

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arm: cache_v7: optimise dcache inval for unaligned range

- inval: flush first and last cacheline
- disable range alignment check(noisy vebose)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Cha

arm: cache_v7: optimise dcache inval for unaligned range

- inval: flush first and last cacheline
- disable range alignment check(noisy vebose)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie448c1c97a7ef15e3a10d3c984d5f36350df4eea

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UPSTREAM: arm: armv7: solve issue for timer_rate_hz in arch timer

The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeou

UPSTREAM: arm: armv7: solve issue for timer_rate_hz in arch timer

The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.

With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
(cherry picked from commit 77aace579a9a84c74e99d2e86ecc08b1d9ca402b)
Change-Id: Id289de433e49d396a95e3a72acf210be3a2d910b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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