feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG

Have informal console output at runtime is useful when searching
errors in TF-A.

Change-Id: I56b5c4fc184e571f79d92bd0aa4fc74f

feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG

Have informal console output at runtime is useful when searching
errors in TF-A.

Change-Id: I56b5c4fc184e571f79d92bd0aa4fc74ff4ed6074
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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fix(imx8m): add RDC entries for all missing UARTs

Commit f7434fa13 ("fix(imx8m): ensure domain permissions for the
console") sets RDC domain to Cortex-A only for console UART. But
this only works if

fix(imx8m): add RDC entries for all missing UARTs

Commit f7434fa13 ("fix(imx8m): ensure domain permissions for the
console") sets RDC domain to Cortex-A only for console UART. But
this only works if there is an RDC configuration entry provided.
Add missing RDC entries using the (reset) default value, so
imx_rdc_console_access_enable() can actually configuration domain
access.

Fixes: f7434fa13507 ("fix(imx8m): ensure domain permissions for the console")
Change-Id: I550dbf2b53795ab43839139c455f2468442a3251
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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fix(imx8m): don't reconfigure default region0

The current code and comments can be read as: "The TZC-380 region 0 can
be configured in size and attributes". This is not true, only the
attributes can

fix(imx8m): don't reconfigure default region0

The current code and comments can be read as: "The TZC-380 region 0 can
be configured in size and attributes". This is not true, only the
attributes can be set.

The TZC-380 region 0 is the TZC default (fallback) region. This region
is used if access to a certain DRAM address was done which isn't covered
by any other region (see [1] for more information). Region 0 covers the
complete AXI space from 0x0 to AXI-bus width. The access is secure-only
after reset.

The TZC-380 is not memory alias aware (see [1] for more information) and
due to the DDR controller, the i.MX8M allows memory alias access.

Configuring region 0 as secure + non-secure RW access opens the
potential security risk of allowing access to secure only memory e.g.
TEE memory area if the TEE didn't configure all memory aliases for its
memory. In such case region 0 is used as fallback if an attackers access
the TEE memory via memory aliases.

To fix this don't touch the TZC-380 at all. The TZC-380 is bypassed
by default if a platform doesn't require a TEE. If the platform requires
a TEE, the TEE is the one which knows the secure areas so let the TEE
configure the TZC-380 accordingly.

Furthmore, since commits:
- 0324081af010 ("feat(imx8mp): restrict peripheral access to secure
world")
- 1156c76361c1 ("feat(imx8mm): restrict peripheral access to secure
world")
the access is limited to the TEE too.

[1] https://developer.arm.com/documentation/ddi0431/c

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I0a0f9b5ad0017f38d767f583d7765a2f79861589

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chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
e

chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
expectation so that future platform implementers don't get misled.

Change-Id: Ic33f0b6da74592ad6778fd802c2f0b85223af614
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(imx8m): ensure domain permissions for the console

The commit d76f012ea8fc0 ("refactor(imx8m): replace magic number with
enum type") also hardcodes the domain permissions configuration for the
UA

fix(imx8m): ensure domain permissions for the console

The commit d76f012ea8fc0 ("refactor(imx8m): replace magic number with
enum type") also hardcodes the domain permissions configuration for the
UARTs, causing a regression for any board using a boot console different
from UART2. Indeed, previously, the RDC_PDAP_UARTn registers were set to
the reset value (0xff), meaning all domains were enabled for read and
write access.

This patch fixes this regression by ensuring that the console always has
read/write access enabled for domain 0.

Tested on a i.MX8MN BSH SMM S2 PRO board.

Fixes: d76f012ea8fc0 ("refactor(imx8m): replace magic number with enum type")
Change-Id: I2670bf485372f32ef45cebb72a7694a9a800f417
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

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refactor(imx8m): replace UART base magic numbers with macros

This patch replaces the magic numbers of the UART base addresses with
the corresponding macros defined in the appropriate platform file.

refactor(imx8m): replace UART base magic numbers with macros

This patch replaces the magic numbers of the UART base addresses with
the corresponding macros defined in the appropriate platform file.

Change-Id: Ie6a4555a659e9f722a8d819958ad9a2dee7c3aa0
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

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fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no long

fix(imx): disable DRAM retention by default on i.MX8MQ

Building the default upstream configuration for the imx8mq-evk is no longer
possible: The linker will complain that the TF-A image will no longer
fit On-Chip SRAM.

In order to make the i.MX8MQ Image buildable again, let's make the DRAM
retention feature optional: It was added in v2.9 and it's possible to
boot the systems without it. Users that make space elsewhere and wish to
enable it can use the newly introduced IMX_DRAM_RETENTION parameter to
configure it. The parameter is added to all i.MX8M variants, but only
for i.MX8MQ, we disable it by default, as that's the one that currently
has binary size problems.

Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7
Fixes: dd108c3c1fe3 ("feat(imx8mq): add the dram retention support for imx8mq")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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feat(imx8mn): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if

feat(imx8mn): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.

Change-Id: Ia12d35778f4d550860e517f2a1f5c5d062f3283a
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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feat(imx): add helper to take params from BL2

So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardco

feat(imx): add helper to take params from BL2

So far the i.MX BL31 doesn't take any parameters. This means the BL32
image base address and whether or not a BL32 image is used at all has to
be hardcoded in BL31.

This adds a helper function that allows to take params from BL2 safely.
On i.MX BL2 is usually U-Boot SPL which passes random values in arg0,
so make sure arg0 is within the internal SRAM range before accessing it
as a pointer. Also make sure arg0 is sufficiently aligned and the header
type and version is correct.

Change-Id: Idab8013a1d6dabf50a83c75f3e6f831de4a537e9
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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