| b5b57691 | 17-Apr-2026 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(cpus): add sysreg_lazy_* macros for batched read-modify-write
This patch introduces five assembly macros that collapse multiple
bit-manipulation operations on the same system register into a
si
feat(cpus): add sysreg_lazy_* macros for batched read-modify-write
This patch introduces five assembly macros that collapse multiple
bit-manipulation operations on the same system register into a
single mrs/msr pair:
sysreg_lazy_start _reg -- read register into x1
sysreg_lazy_set _bit -- ORR bit into x1 (any 64-bit mask)
sysreg_lazy_clear _bit -- BIC bit from x1 (any 64-bit mask)
sysreg_lazy_insert _src, _lsb, _width -- BFI into x1
sysreg_lazy_commit _reg -- write x1 back to register
Each sysreg_bit_set / sysreg_bit_clear / sysreg_bitfield_insert call
issues its own mrs+msr pair. When several of those target the same
register the reads and writes are redundant. The lazy helpers
replace N reads and N writes with one read and one write.
x1 holds the accumulated register value between start and commit.
x0 is used as a scratch register by sysreg_lazy_set,
sysreg_lazy_clear, and sysreg_lazy_insert. mov_imm is used for bit
values to support arbitrary 64-bit masks, consistent with the
existing hand-written mrs/mov_imm/orr/msr patterns in CPU files.
Change-Id: Iaaf0e4bd7ba85c69d9063b012a9066b3ba40b58e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 874d48d8 | 27-Feb-2026 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-A77 erratum 1515815
Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.
Set CPUACTLR_EL1[11] to 1 so that the L
fix(cpus): workaround for Cortex-A77 erratum 1515815
Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.
Set CPUACTLR_EL1[11] to 1 so that the L0 Macro-op cache is flushed for
all context synchronization events, ensuring that only a single
instruction is executed before a software step or halt step exception
is taken.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest
Change-Id: I1e6faf5a699734f9a5be848807e9c3fa5110d569
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 9b73520c | 27-Feb-2026 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-A77 erratum 1253791
Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.
This erratum can be avoided by setting CPUACTL
fix(cpus): workaround for Cortex-A77 erratum 1253791
Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR3_EL1[10] to 1, which
prevents parallel execution of divide and square root instructions.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest
Change-Id: I76895d167a477246ff5bc6c87237fb4f9724c547
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 183e1d79 | 27-Feb-2026 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-A78AE erratum 2779481
Cortex-A78AE erratum 2779481 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.
The erratum can be avoided by
fix(cpus): workaround for Cortex-A78AE erratum 2779481
Cortex-A78AE erratum 2779481 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.
The erratum can be avoided by setting CPUACTLR3_EL1[47].
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest
Change-Id: If45cd8efe24768aaa0d31f56b3b297ba1c10980f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 691334aa | 27-Feb-2026 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Neoverse V1 erratum 1619807
Neoverse V1 erratum 1619807 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
Set CPUACTLR_EL1 bit 11 to 1 so that all con
fix(cpus): workaround for Neoverse V1 erratum 1619807
Neoverse V1 erratum 1619807 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
Set CPUACTLR_EL1 bit 11 to 1 so that all context synchronization
events flush the L0 Macro-op cache, ensuring that when software step
or halt step is enabled the core takes the exception after the
intended single instruction rather than after multiple instructions
from the L0 Macro-op cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest
Change-Id: Ie9595ccbcba04892ebfbfffc067bc2fe1b5a1e6e
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| dca40b8d | 19-Dec-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-X925 erratum 3865185
Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.
Load issued to Non-Cacheable or De
fix(cpus): workaround for Cortex-X925 erratum 3865185
Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.
Load issued to Non-Cacheable or Device GRE memory can
read stale data brought in by an earlier load to the
same cache-line thereby violating ordering requirements.
This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.
SDEN documentation:
https://developer.arm.com/documentation/109180/latest/
Change-Id: Iff224ef82bd1cb9aff8d6b11451e2ac1d048149f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| ea24488d | 19-Dec-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-X925 erratum 3730893
Cortex-X925 erratum 3730893 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.
PE executing a load instruction th
fix(cpus): workaround for Cortex-X925 erratum 3730893
Cortex-X925 erratum 3730893 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.
PE executing a load instruction that accesses a memory
region which crosses a 4K boundary might cause a deadlock.
This erratum can be avoided by setting CPUACTLR_EL1[60:58]
to 3'b001, which has a small perf impact.
SDEN documentation:
https://developer.arm.com/documentation/109180/latest/
Change-Id: I0245183669255afb0d3ec71cafa058aa72129de0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 7c00052c | 19-Dec-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-X925 erratum 2922378
Cortex-X925 erratum 2922378 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.
Branch prediction history is not suppressed when swit
fix(cpus): workaround for Cortex-X925 erratum 2922378
Cortex-X925 erratum 2922378 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.
Branch prediction history is not suppressed when switching from low
to high EL, this erratum can be avoided by setting the CPUACTLR4[10]
to 1 and CPUACTLR4[11] to 1.
SDEN documentation:
https://developer.arm.com/documentation/109180/latest/
Change-Id: Ieb5fe278821d85382af60be25e9546e65ba9a629
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 89725bc3 | 19-Dec-2025 |
Xialin Liu <xialin.liu@arm.com> |
fix(cpus): workaround for Cortex-X925 erratum 2921199
Cortex-X925 erratum 2921199 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.
Under certain rare microarchitectural conditions, two
fix(cpus): workaround for Cortex-X925 erratum 2921199
Cortex-X925 erratum 2921199 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.
Under certain rare microarchitectural conditions, two or more STG
instructions that access the same cache line but different 32-bytes
might not write the MTE allocation tag to memory. This erratum can
be avoided by setting CPUACTLR5_EL1[14] to 1.
SDEN documentation:
https://developer.arm.com/documentation/109180/latest/
Change-Id: I8eb8bbdd6f99f69c8713400191ac66f55ffedc8b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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