1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 45 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 46workaround_reset_end c1_pro, ERRATUM(3706576) 47 48check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 49 50cpu_reset_func_start c1_pro 51 /* ---------------------------------------------------- 52 * Disable speculative loads 53 * ---------------------------------------------------- 54 */ 55 msr SSBS, xzr 56 /* model bug: not cleared on reset */ 57 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 58 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 59 enable_mpmm 60cpu_reset_func_end c1_pro 61 62 /* ---------------------------------------------------- 63 * HW will do the cache maintenance while powering down 64 * ---------------------------------------------------- 65 */ 66func c1_pro_core_pwr_dwn 67 /* --------------------------------------------------- 68 * Flip CPU power down bit in power control register. 69 * It will be set on powerdown and cleared on wakeup 70 * --------------------------------------------------- 71 */ 72 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 73 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 74 isb 75 signal_pabandon_handled 76 ret 77endfunc c1_pro_core_pwr_dwn 78 79 /* --------------------------------------------- 80 * This function provides Arm C1-Pro specific 81 * register information for crash reporting. 82 * It needs to return with x6 pointing to 83 * a list of register names in ascii and 84 * x8 - x15 having values of registers to be 85 * reported. 86 * --------------------------------------------- 87 */ 88.section .rodata.c1_pro_regs, "aS" 89c1_pro_regs: /* The ASCII list of register names to be reported */ 90 .asciz "imp_cpuectlr_el1", "" 91 92func c1_pro_cpu_reg_dump 93 adr x6, c1_pro_regs 94 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 95 ret 96endfunc c1_pro_cpu_reg_dump 97 98declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 99 c1_pro_reset_func, \ 100 c1_pro_core_pwr_dwn 101