1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_ultra.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Ultra must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Ultra supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Ultra needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_ultra 30 31 /* ------------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Ultra using erratum 3651221 33 * workaround by disabling the affected prefetcher setting 34 * CPUACTLR6_EL1[41]. 35 * ------------------------------------------------------------- 36 */ 37workaround_reset_start c1_ultra, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 39workaround_reset_end c1_ultra, CVE(2024, 7881) 40 41check_erratum_ls c1_ultra, CVE(2024, 7881), CPU_REV(0, 0) 42 43workaround_reset_start c1_ultra, ERRATUM(3502731), ERRATA_C1ULTRA_3502731 44 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 45workaround_reset_end c1_ultra, ERRATUM(3502731) 46 47check_erratum_ls c1_ultra, ERRATUM(3502731), CPU_REV(0, 0) 48 49workaround_reset_start c1_ultra, ERRATUM(3651221), ERRATA_C1ULTRA_3651221 50 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 51workaround_reset_end c1_ultra, ERRATUM(3651221) 52 53check_erratum_ls c1_ultra, ERRATUM(3651221), CPU_REV(0, 0) 54 55workaround_reset_start c1_ultra, ERRATUM(3684152), ERRATA_C1ULTRA_3684152 56 sysreg_bitfield_insert C1_ULTRA_IMP_CPUACTLR_EL1, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_BIT, \ 57 C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_WIDTH 58workaround_reset_end c1_ultra, ERRATUM(3684152) 59 60check_erratum_ls c1_ultra, ERRATUM(3684152), CPU_REV(0, 0) 61 62workaround_reset_start c1_ultra, ERRATUM(3705939), ERRATA_C1ULTRA_3705939 63 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR_EL1, BIT(48) 64workaround_reset_end c1_ultra, ERRATUM(3705939) 65 66check_erratum_ls c1_ultra, ERRATUM(3705939), CPU_REV(1, 0) 67 68workaround_reset_start c1_ultra, ERRATUM(3815514), ERRATA_C1ULTRA_3815514 69 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR5_EL1, BIT(13) 70workaround_reset_end c1_ultra, ERRATUM(3815514) 71 72check_erratum_ls c1_ultra, ERRATUM(3815514), CPU_REV(1, 0) 73 74workaround_reset_start c1_ultra, ERRATUM(3865171), ERRATA_C1ULTRA_3865171 75 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR2_EL1, BIT(22) 76workaround_reset_end c1_ultra, ERRATUM(3865171) 77 78check_erratum_ls c1_ultra, ERRATUM(3865171), CPU_REV(1, 0) 79 80cpu_reset_func_start c1_ultra 81 /* ---------------------------------------------------- 82 * Disable speculative loads 83 * ---------------------------------------------------- 84 */ 85 msr SSBS, xzr 86 /* model bug: not cleared on reset */ 87 sysreg_bit_clear C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 88 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 89 enable_mpmm 90cpu_reset_func_end c1_ultra 91 92func c1_ultra_core_pwr_dwn 93 /* --------------------------------------------------- 94 * Flip CPU power down bit in power control register. 95 * It will be set on powerdown and cleared on wakeup 96 * --------------------------------------------------- 97 */ 98 sysreg_bit_toggle C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 99 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 100 isb 101 signal_pabandon_handled 102 ret 103endfunc c1_ultra_core_pwr_dwn 104 105.section .rodata.c1_ultra_regs, "aS" 106c1_ultra_regs: /* The ASCII list of register names to be reported */ 107 .asciz "cpuectlr_el1", "" 108 109func c1_ultra_cpu_reg_dump 110 adr x6, c1_ultra_regs 111 mrs x8, C1_ULTRA_IMP_CPUECTLR_EL1 112 ret 113endfunc c1_ultra_cpu_reg_dump 114 115declare_cpu_ops c1_ultra, C1_ULTRA_MIDR, \ 116 c1_ultra_reset_func, \ 117 c1_ultra_core_pwr_dwn 118