1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 45 mov x0, #5 46 msr C1_PRO_IMP_CPUPSELR_EL3, x0 47 isb 48 ldr x0, =0xd503329f 49 msr C1_PRO_IMP_CPUPOR_EL3, x0 50 ldr x0, =0xfffff3ff 51 msr C1_PRO_IMP_CPUPMR_EL3, x0 52 mov x1, #0 53 orr x1, x1, #1<<0 54 orr x1, x1, #3<<4 55 orr x1, x1, #0xf<<6 56 orr x1, x1, #1<<22 57 orr x1, x1, #1<<32 58 msr C1_PRO_IMP_CPUPCR_EL3, x1 59workaround_reset_end c1_pro, ERRATUM(3694158) 60 61check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 62 63workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 64 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 65workaround_reset_end c1_pro, ERRATUM(3706576) 66 67check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 68 69cpu_reset_func_start c1_pro 70 /* ---------------------------------------------------- 71 * Disable speculative loads 72 * ---------------------------------------------------- 73 */ 74 msr SSBS, xzr 75 /* model bug: not cleared on reset */ 76 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 77 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 78 enable_mpmm 79cpu_reset_func_end c1_pro 80 81 /* ---------------------------------------------------- 82 * HW will do the cache maintenance while powering down 83 * ---------------------------------------------------- 84 */ 85func c1_pro_core_pwr_dwn 86 /* --------------------------------------------------- 87 * Flip CPU power down bit in power control register. 88 * It will be set on powerdown and cleared on wakeup 89 * --------------------------------------------------- 90 */ 91 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 92 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 93 isb 94 signal_pabandon_handled 95 ret 96endfunc c1_pro_core_pwr_dwn 97 98 /* --------------------------------------------- 99 * This function provides Arm C1-Pro specific 100 * register information for crash reporting. 101 * It needs to return with x6 pointing to 102 * a list of register names in ascii and 103 * x8 - x15 having values of registers to be 104 * reported. 105 * --------------------------------------------- 106 */ 107.section .rodata.c1_pro_regs, "aS" 108c1_pro_regs: /* The ASCII list of register names to be reported */ 109 .asciz "imp_cpuectlr_el1", "" 110 111func c1_pro_cpu_reg_dump 112 adr x6, c1_pro_regs 113 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 114 ret 115endfunc c1_pro_cpu_reg_dump 116 117declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 118 c1_pro_reset_func, \ 119 c1_pro_core_pwr_dwn 120