1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_premium.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Premium must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Premium supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Premium needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_premium 30 31 /* --------------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Premium using erratum 3651221 33 * workaround by disabling the affected prefetcher setting 34 * CPUACTLR6_EL1[41]. 35 * --------------------------------------------------------------- 36 */ 37workaround_reset_start c1_premium, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41) 39workaround_reset_end c1_premium, CVE(2024, 7881) 40 41check_erratum_ls c1_premium, CVE(2024, 7881), CPU_REV(0, 0) 42 43workaround_reset_start c1_premium, ERRATUM(3502731), ERRATA_C1PREMIUM_3502731 44 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 45workaround_reset_end c1_premium, ERRATUM(3502731) 46 47check_erratum_ls c1_premium, ERRATUM(3502731), CPU_REV(0, 0) 48 49cpu_reset_func_start c1_premium 50 /* Disable speculative loads */ 51 msr SSBS, xzr 52 enable_mpmm 53cpu_reset_func_end c1_premium 54 55func c1_premium_core_pwr_dwn 56 /* --------------------------------------------------- 57 * Flip CPU power down bit in power control register. 58 * It will be set on powerdown and cleared on wakeup. 59 * --------------------------------------------------- 60 */ 61 sysreg_bit_toggle C1_PREMIUM_IMP_CPUPWRCTLR_EL1, \ 62 C1_PREMIUM_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 63 isb 64 signal_pabandon_handled 65 ret 66endfunc c1_premium_core_pwr_dwn 67 68.section .rodata.c1_premium_regs, "aS" 69c1_premium_regs: /* The ASCII list of register names to be reported */ 70 .asciz "cpuectlr_el1", "" 71 72func c1_premium_cpu_reg_dump 73 adr x6, c1_premium_regs 74 mrs x8, C1_PREMIUM_IMP_CPUECTLR_EL1 75 ret 76endfunc c1_premium_cpu_reg_dump 77 78declare_cpu_ops c1_premium, C1_PREMIUM_MIDR, \ 79 c1_premium_reset_func, \ 80 c1_premium_core_pwr_dwn 81