1 /* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef C1_ULTRA_H 8 #define C1_ULTRA_H 9 10 #define C1_ULTRA_MIDR U(0x410FD8C0) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define C1_ULTRA_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16 17 /******************************************************************************* 18 * CPU Power Control register specific definitions 19 ******************************************************************************/ 20 #define C1_ULTRA_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21 #define C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22 23 /******************************************************************************* 24 * CPU Auxiliary Control register specific definitions 25 ******************************************************************************/ 26 #define C1_ULTRA_IMP_CPUACTLR_EL1 S3_0_C15_C1_0 27 #define C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_BIT U(1) 28 #define C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_SHIFT U(58) 29 #define C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_WIDTH U(3) 30 #define C1_ULTRA_IMP_CPUACTLR4_EL1 S3_0_C15_C1_3 31 #define C1_ULTRA_IMP_CPUACTLR6_EL1 S3_0_C15_C8_1 32 33 #endif /* C1_ULTRA_H */ 34