1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_reset_start c1_pro, ERRATUM(3684268), ERRATA_C1PRO_3684268 45 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 46 dsb sy 47workaround_reset_end c1_pro, ERRATUM(3684268) 48 49check_erratum_ls c1_pro, ERRATUM(3684268), CPU_REV(1, 0) 50 51workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 52 mov x0, #5 53 msr C1_PRO_IMP_CPUPSELR_EL3, x0 54 isb 55 ldr x0, =0xd503329f 56 msr C1_PRO_IMP_CPUPOR_EL3, x0 57 ldr x0, =0xfffff3ff 58 msr C1_PRO_IMP_CPUPMR_EL3, x0 59 mov x1, #0 60 orr x1, x1, #1<<0 61 orr x1, x1, #3<<4 62 orr x1, x1, #0xf<<6 63 orr x1, x1, #1<<22 64 orr x1, x1, #1<<32 65 msr C1_PRO_IMP_CPUPCR_EL3, x1 66workaround_reset_end c1_pro, ERRATUM(3694158) 67 68check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 69 70workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 71 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 72workaround_reset_end c1_pro, ERRATUM(3706576) 73 74check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 75 76cpu_reset_func_start c1_pro 77 /* ---------------------------------------------------- 78 * Disable speculative loads 79 * ---------------------------------------------------- 80 */ 81 msr SSBS, xzr 82 /* model bug: not cleared on reset */ 83 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 84 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 85 enable_mpmm 86cpu_reset_func_end c1_pro 87 88 /* ---------------------------------------------------- 89 * HW will do the cache maintenance while powering down 90 * ---------------------------------------------------- 91 */ 92func c1_pro_core_pwr_dwn 93 /* --------------------------------------------------- 94 * Flip CPU power down bit in power control register. 95 * It will be set on powerdown and cleared on wakeup 96 * --------------------------------------------------- 97 */ 98 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 99 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 100 isb 101 signal_pabandon_handled 102 ret 103endfunc c1_pro_core_pwr_dwn 104 105 /* --------------------------------------------- 106 * This function provides Arm C1-Pro specific 107 * register information for crash reporting. 108 * It needs to return with x6 pointing to 109 * a list of register names in ascii and 110 * x8 - x15 having values of registers to be 111 * reported. 112 * --------------------------------------------- 113 */ 114.section .rodata.c1_pro_regs, "aS" 115c1_pro_regs: /* The ASCII list of register names to be reported */ 116 .asciz "imp_cpuectlr_el1", "" 117 118func c1_pro_cpu_reg_dump 119 adr x6, c1_pro_regs 120 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 121 ret 122endfunc c1_pro_cpu_reg_dump 123 124declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 125 c1_pro_reset_func, \ 126 c1_pro_core_pwr_dwn 127