1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a725 26 27.global check_erratum_cortex_a725_3699564 28 29#if ENABLE_SPE_FOR_NS 30workaround_reset_start cortex_a725, ERRATUM(2874943), ERRATA_A725_2874943 31 sysreg_bit_set CORTEX_A725_CPUACTLR_EL1, BIT(57) 32 sysreg_bit_set CORTEX_A725_CPUACTLR_EL1, BIT(58) 33workaround_reset_end cortex_a725, ERRATUM(2874943) 34 35check_erratum_ls cortex_a725, ERRATUM(2874943), CPU_REV(0, 0) 36#endif 37 38workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952 39 errata_dsu_2900952_wa_apply 40workaround_reset_end cortex_a725, ERRATUM(2900952) 41 42check_erratum_custom_start cortex_a725, ERRATUM(2900952) 43 check_errata_dsu_2900952_applies 44 ret 45check_erratum_custom_end cortex_a725, ERRATUM(2900952) 46 47workaround_reset_start cortex_a725, ERRATUM(2936490), ERRATA_A725_2936490 48 sysreg_bit_set CORTEX_A725_CPUACTLR2_EL1, BIT(37) 49workaround_reset_end cortex_a725, ERRATUM(2936490) 50 51check_erratum_ls cortex_a725, ERRATUM(2936490), CPU_REV(0, 0) 52 53add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564 54 55check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) 56 57workaround_reset_start cortex_a725, ERRATUM(3711914), ERRATA_A725_3711914 58 mov x0, #5 59 msr CORTEX_A725_CPUPSELR_EL3, x0 60 isb 61 62 ldr x0, =0xd503329f 63 msr CORTEX_A725_CPUPOR_EL3, x0 64 ldr x0, =0xfffff3ff 65 msr CORTEX_A725_CPUPMR_EL3, x0 66 mov x1, #0 67 orr x1, x1, #(1<<0) 68 orr x1, x1, #(3<<4) 69 orr x1, x1, #(0xf<<6) 70 orr x1, x1, #(1<<22) 71 orr x1, x1, #(1<<32) 72 msr CORTEX_A725_CPUPCR_EL3, x1 73 isb 74workaround_reset_end cortex_a725, ERRATUM(3711914) 75 76check_erratum_ls cortex_a725, ERRATUM(3711914), CPU_REV(0, 1) 77 78cpu_reset_func_start cortex_a725 79 /* Disable speculative loads */ 80 msr SSBS, xzr 81 enable_mpmm 82cpu_reset_func_end cortex_a725 83 84 /* ---------------------------------------------------- 85 * HW will do the cache maintenance while powering down 86 * ---------------------------------------------------- 87 */ 88func cortex_a725_core_pwr_dwn 89 /* --------------------------------------------------- 90 * Enable CPU power down bit in power control register 91 * --------------------------------------------------- 92 */ 93 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 94 isb 95 ret 96endfunc cortex_a725_core_pwr_dwn 97 98 /* --------------------------------------------- 99 * This function provides Cortex-A725 specific 100 * register information for crash reporting. 101 * It needs to return with x6 pointing to 102 * a list of register names in ascii and 103 * x8 - x15 having values of registers to be 104 * reported. 105 * --------------------------------------------- 106 */ 107.section .rodata.cortex_a725_regs, "aS" 108cortex_a725_regs: /* The ascii list of register names to be reported */ 109 .asciz "cpuectlr_el1", "" 110 111func cortex_a725_cpu_reg_dump 112 adr x6, cortex_a725_regs 113 mrs x8, CORTEX_A725_CPUECTLR_EL1 114 ret 115endfunc cortex_a725_cpu_reg_dump 116 117declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 118 cortex_a725_reset_func, \ 119 cortex_a725_core_pwr_dwn 120