feat(tc): add SLC MSC nodes to TC4 DT

These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.

feat(tc): add SLC MSC nodes to TC4 DT

These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312

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refactor(tc): clarify msc0 DT node

This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@a

refactor(tc): clarify msc0 DT node

This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4

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feat(tc): update CPU PMU nodes for tc4

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU node per microarchitecture.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

feat(tc): update CPU PMU nodes for tc4

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU node per microarchitecture.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibbe8dacda695ccb45965c7f4680d4b03cffdb815

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Merge changes I95bb84b0,I2dfa62ac,I4017e44b into integration

* changes:
feat(stm32mp2-fdts): add STM32MP257F-DK board support
fix(stm32mp2-fdts): fix SDMMC slew rate
feat(stm32mp2-fdts): add L

Merge changes I95bb84b0,I2dfa62ac,I4017e44b into integration

* changes:
feat(stm32mp2-fdts): add STM32MP257F-DK board support
fix(stm32mp2-fdts): fix SDMMC slew rate
feat(stm32mp2-fdts): add LPDDR4 files

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Merge changes I10a3fc1d,I3aed6228 into integration

* changes:
fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu
fix(tc): fix SMMU streamId for tc4 gpu

refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a70

refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM

Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.

Change-Id: I70b68b06501d17dcebbe78bee8fec0a701106c92
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify ethernet configuration for TC4 FPGA

Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: I7b180c3eb90d7557d0011a25a742106f70

fix(tc): modify ethernet configuration for TC4 FPGA

Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: I7b180c3eb90d7557d0011a25a742106f703cd264
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1

fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd4899459358299

fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify mmc configuration for TC4 FPGA

Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Sig

fix(tc): modify mmc configuration for TC4 FPGA

Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu

As per GPU team, this change should be helpful to improve
the performance.

Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-b

fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu

As per GPU team, this change should be helpful to improve
the performance.

Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): fix SMMU streamId for tc4 gpu

Currently used stream id 0x200 gives below fault,

[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000

fix(tc): fix SMMU streamId for tc4 gpu

Currently used stream id 0x200 gives below fault,

[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000000000
[ 9.547393][ C0] raw fault status: 0x400D02C0
[ 9.547393][ C0] exception type 0xC0: TRANSLATION_FAULT at level 0
[ 9.547393][ C0] access type 0x2: READ

As per the GPU team, GPU stream id is 0 on TC4-FPGA so change it.

Change-Id: I3aed62289c5b96fb850f0022ea7f5172c606eb95
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagd

refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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feat(stm32mp2-fdts): add STM32MP257F-DK board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI

feat(stm32mp2-fdts): add STM32MP257F-DK board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LVDS connector ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Olivier BIDEAU <olivier.bideau@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I95bb84b00eafce8031f26f7243ecc0fce843d170

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fix(stm32mp2-fdts): fix SDMMC slew rate

New slew rate applied.

SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.

SDMMC

fix(stm32mp2-fdts): fix SDMMC slew rate

New slew rate applied.

SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.

SDMMC1:
- for dk board:
- clk at 2.
- cmd and data at 1.
- for eval board:
- clk at 3.
- cmd and data at 2.

Change-Id: I2dfa62aca08a613e0532746050246fc8dc476ff8
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>

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feat(stm32mp2-fdts): add LPDDR4 files

These DT files will be used by STM32MP2 boards. They embed DDR
parameters for LPDDR4 1x16Gb 1*32bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.g

feat(stm32mp2-fdts): add LPDDR4 files

These DT files will be used by STM32MP2 boards. They embed DDR
parameters for LPDDR4 1x16Gb 1*32bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4017e44b3e9d01735d76518666d05405c2bd976b

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Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure acc

Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4

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feat(tc): add MCN PMU nodes in dts for TC4

Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zey

feat(tc): add MCN PMU nodes in dts for TC4

Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251

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feat(tc): add 'kaslr-seed' node in device tree for TC3

Add 'kaslr-seed' node in device tree for TC3.

Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's

feat(tc): add 'kaslr-seed' node in device tree for TC3

Add 'kaslr-seed' node in device tree for TC3.

Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's RNG_TRAP feature.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5c3f857d0f4e81ccd3bacb4c1ab032c8ea6e6873

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fix(stm32mp1-fdts): re-enable RTC clock

On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.

Signed-off-by: Valentin

fix(stm32mp1-fdts): re-enable RTC clock

On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7

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Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration

feat(tc): add devicetree node for AP/RSE MHU

These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are us

feat(tc): add devicetree node for AP/RSE MHU

These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are used to
communicate with RSE so keep rse mhu disabled for fpga.

Signed-off-by: Yu Shihai <yu.shihai@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib10b3da09626e5beb6d6cd87b1618a143234a5d0

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feat(tc): add dsu pmu node for TC4

Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-

feat(tc): add dsu pmu node for TC4

Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib1b810df65004987e9f3cf1bbd5deb5d211f3a17

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Merge "fix(rd1ae): fix rd1-ae device tree" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

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