1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&CPU0>; 57 }; 58 core1 { 59 cpu = <&CPU1>; 60 }; 61 core2 { 62 cpu = <&CPU2>; 63 }; 64 core3 { 65 cpu = <&CPU3>; 66 }; 67 core4 { 68 cpu = <&CPU4>; 69 }; 70 core5 { 71 cpu = <&CPU5>; 72 }; 73 core6 { 74 cpu = <&CPU6>; 75 }; 76 core7 { 77 cpu = <&CPU7>; 78 }; 79 }; 80 }; 81 82 /* 83 * The timings below are just to demonstrate working cpuidle. 84 * These values may be inaccurate. 85 */ 86 idle-states { 87 entry-method = "psci"; 88 89 CPU_SLEEP_0: cpu-sleep-0 { 90 compatible = "arm,idle-state"; 91 arm,psci-suspend-param = <0x0010000>; 92 local-timer-stop; 93 entry-latency-us = <300>; 94 exit-latency-us = <1200>; 95 min-residency-us = <2000>; 96 }; 97 CLUSTER_SLEEP_0: cluster-sleep-0 { 98 compatible = "arm,idle-state"; 99 arm,psci-suspend-param = <0x1010000>; 100 local-timer-stop; 101 entry-latency-us = <400>; 102 exit-latency-us = <1200>; 103 min-residency-us = <2500>; 104 }; 105 }; 106 107 amus { 108 amu: amu-0 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 mpmm_gear0: counter@0 { 113 reg = <0>; 114 enable-at-el3; 115 }; 116 117 mpmm_gear1: counter@1 { 118 reg = <1>; 119 enable-at-el3; 120 }; 121 122 mpmm_gear2: counter@2 { 123 reg = <2>; 124 enable-at-el3; 125 }; 126 }; 127 }; 128 129 CPU0:cpu@0 { 130 device_type = "cpu"; 131 compatible = "arm,armv8"; 132 reg = <0x0>; 133 enable-method = "psci"; 134 clocks = <&scmi_dvfs 0>; 135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 capacity-dmips-mhz = <LIT_CAPACITY>; 137 amu = <&amu>; 138 }; 139 140 CPU1:cpu@100 { 141 device_type = "cpu"; 142 compatible = "arm,armv8"; 143 reg = <0x100>; 144 enable-method = "psci"; 145 clocks = <&scmi_dvfs 0>; 146 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 147 capacity-dmips-mhz = <LIT_CAPACITY>; 148 amu = <&amu>; 149 }; 150 151 CPU2:cpu@200 { 152 device_type = "cpu"; 153 compatible = "arm,armv8"; 154 reg = <0x200>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 157 amu = <&amu>; 158 }; 159 160 CPU3:cpu@300 { 161 device_type = "cpu"; 162 compatible = "arm,armv8"; 163 reg = <0x300>; 164 enable-method = "psci"; 165 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 166 amu = <&amu>; 167 }; 168 169 CPU4:cpu@400 { 170 device_type = "cpu"; 171 compatible = "arm,armv8"; 172 reg = <0x400>; 173 enable-method = "psci"; 174 clocks = <&scmi_dvfs 1>; 175 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 176 capacity-dmips-mhz = <MID_CAPACITY>; 177 amu = <&amu>; 178 }; 179 180 CPU5:cpu@500 { 181 device_type = "cpu"; 182 compatible = "arm,armv8"; 183 reg = <0x500>; 184 enable-method = "psci"; 185 clocks = <&scmi_dvfs 1>; 186 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 187 capacity-dmips-mhz = <MID_CAPACITY>; 188 amu = <&amu>; 189 }; 190 191 CPU6:cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,armv8"; 194 reg = <0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 197 amu = <&amu>; 198 }; 199 200 CPU7:cpu@700 { 201 device_type = "cpu"; 202 compatible = "arm,armv8"; 203 reg = <0x700>; 204 enable-method = "psci"; 205 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 206 amu = <&amu>; 207 }; 208 }; 209 210 reserved-memory { 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 215 linux,cma { 216 compatible = "shared-dma-pool"; 217 reusable; 218 size = <0x0 0x8000000>; 219 linux,cma-default; 220 }; 221 222 optee { 223 compatible = "restricted-dma-pool"; 224 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 225 }; 226 227 }; 228 229 memory { 230 device_type = "memory"; 231 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 232 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 233 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 234 }; 235 236 psci { 237 compatible = "arm,psci-1.0", "arm,psci-0.2"; 238 method = "smc"; 239 }; 240 241 cpu-pmu-little { 242 compatible = LIT_CPU_PMU_COMPATIBLE; 243 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>; 244 status = "okay"; 245 }; 246 247 cpu-pmu-mid { 248 compatible = MID_CPU_PMU_COMPATIBLE; 249 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 250 status = "okay"; 251 }; 252 253 cpu-pmu-big { 254 compatible = BIG_CPU_PMU_COMPATIBLE; 255 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 256 status = "okay"; 257 }; 258 259 sram: sram@6000000 { 260 compatible = "mmio-sram"; 261 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 262 263 #address-cells = <1>; 264 #size-cells = <1>; 265 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 266 267 cpu_scp_scmi_a2p: scp-shmem@0 { 268 compatible = "arm,scmi-shmem"; 269 reg = <0x0 0x80>; 270 }; 271 }; 272 273 mbox_db_rx: mhu@MHU_RX_ADDR { 274 compatible = MHU_RX_COMPAT; 275 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>; 276 clocks = <&soc_refclk>; 277 clock-names = "apb_pclk"; 278 #mbox-cells = <MHU_MBOX_CELLS>; 279 interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>; 280 interrupt-names = MHU_RX_INT_NAME; 281 }; 282 283 mbox_db_tx: mhu@MHU_TX_ADDR { 284 compatible = MHU_TX_COMPAT; 285 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>; 286 clocks = <&soc_refclk>; 287 clock-names = "apb_pclk"; 288 #mbox-cells = <MHU_MBOX_CELLS>; 289 interrupt-names = MHU_TX_INT_NAME; 290 }; 291 292 firmware { 293 scmi { 294 compatible = "arm,scmi"; 295 mbox-names = "tx", "rx"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299#if TC_SCMI_PD_CTRL_EN 300 scmi_devpd: protocol@11 { 301 reg = <0x11>; 302 #power-domain-cells = <1>; 303 }; 304#endif /* TC_SCMI_PD_CTRL_EN */ 305 306 scmi_dvfs: protocol@13 { 307 reg = <0x13>; 308 #clock-cells = <1>; 309 }; 310 311 scmi_clk: protocol@14 { 312 reg = <0x14>; 313 #clock-cells = <1>; 314 }; 315 }; 316 }; 317 318 gic: interrupt-controller@GIC_CTRL_ADDR { 319 compatible = "arm,gic-v3"; 320 #address-cells = <2>; 321 #interrupt-cells = <4>; 322 #size-cells = <2>; 323 ranges; 324 interrupt-controller; 325 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 326 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 327 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>; 328 }; 329 330 timer { 331 compatible = "arm,armv8-timer"; 332 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 333 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 334 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 335 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 336 }; 337 338 spe-pmu-mid { 339 compatible = "arm,statistical-profiling-extension-v1"; 340 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>; 341 status = "disabled"; 342 }; 343 344 spe-pmu-big { 345 compatible = "arm,statistical-profiling-extension-v1"; 346 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>; 347 status = "disabled"; 348 }; 349 350 soc_refclk: refclk { 351 compatible = "fixed-clock"; 352 #clock-cells = <0>; 353 clock-frequency = <1000000000>; 354 clock-output-names = "apb_pclk"; 355 }; 356 357 soc_refclk60mhz: refclk60mhz { 358 compatible = "fixed-clock"; 359 #clock-cells = <0>; 360 clock-frequency = <60000000>; 361 clock-output-names = "iofpga_clk"; 362 }; 363 364 soc_uartclk: uartclk { 365 compatible = "fixed-clock"; 366 #clock-cells = <0>; 367 clock-frequency = <TC_UARTCLK>; 368 clock-output-names = "uartclk"; 369 }; 370 371 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 372 os_uart: serial@2a400000 { 373 compatible = "arm,pl011", "arm,primecell"; 374 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 375 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>; 376 clocks = <&soc_uartclk>, <&soc_refclk>; 377 clock-names = "uartclk", "apb_pclk"; 378 status = "okay"; 379 }; 380 381#if !TC_DPU_USE_SCMI_CLK 382 dpu_aclk: dpu_aclk { 383 compatible = "fixed-clock"; 384 #clock-cells = <0>; 385 clock-frequency = <LCD_TIMING_CLK>; 386 clock-output-names = "fpga:dpu_aclk"; 387 }; 388 389 dpu_pixel_clk: dpu-pixel-clk { 390 compatible = "fixed-clock"; 391 #clock-cells = <0>; 392 clock-frequency = <LCD_TIMING_CLK>; 393 clock-output-names = "pxclk"; 394 }; 395#endif /* !TC_DPU_USE_SCMI_CLK */ 396 397#if TC_DPU_USE_SIMPLE_PANEL 398 vpanel { 399 compatible = "panel-dpi"; 400 post-init-providers = <&pl0>; 401 port { 402 lcd_in: endpoint { 403 remote-endpoint = <&dp_pl0_out0>; 404 }; 405 }; 406 407 panel-timing { 408 LCD_TIMING; 409 }; 410 }; 411 412#else 413 vencoder { 414 compatible = "drm,virtual-encoder"; 415 port { 416 lcd_in: endpoint { 417 remote-endpoint = <&dp_pl0_out0>; 418 }; 419 }; 420 421 display-timings { 422 timing-panel { 423 LCD_TIMING; 424 }; 425 }; 426 427 }; 428#endif 429 ethernet: ethernet@ETHERNET_ADDR { 430 reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>; 431 interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>; 432 433 reg-io-width = <2>; 434 smsc,irq-push-pull; 435 }; 436 437 bp_clock24mhz: clock24mhz { 438 compatible = "fixed-clock"; 439 #clock-cells = <0>; 440 clock-frequency = <24000000>; 441 clock-output-names = "bp:clock24mhz"; 442 }; 443 444 sysreg: sysreg@SYS_REGS_ADDR { 445 compatible = "arm,vexpress-sysreg"; 446 reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 }; 450 451 fixed_3v3: v2m-3v3 { 452 compatible = "regulator-fixed"; 453 regulator-name = "3V3"; 454 regulator-min-microvolt = <3300000>; 455 regulator-max-microvolt = <3300000>; 456 regulator-always-on; 457 }; 458 459 mmci: mmci@MMC_ADDR { 460 compatible = "arm,pl180", "arm,primecell"; 461 reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>; 462 interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>, 463 <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>; 464 wp-gpios = <&sysreg 1 0>; 465 bus-width = <4>; 466 max-frequency = <25000000>; 467 vmmc-supply = <&fixed_3v3>; 468 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 469 clock-names = "mclk", "apb_pclk"; 470 }; 471 472 gpu_clk: gpu_clk { 473 compatible = "fixed-clock"; 474 #clock-cells = <0>; 475 clock-frequency = <1000000000>; 476 }; 477 478 gpu_core_clk: gpu_core_clk { 479 compatible = "fixed-clock"; 480 #clock-cells = <0>; 481 clock-frequency = <1000000000>; 482 }; 483 484 gpu: gpu@2d000000 { 485 compatible = "arm,mali-midgard"; 486 reg = <0x0 0x2d000000 0x0 0x200000>; 487 clocks = <&gpu_core_clk>; 488 clock-names = "shadercores"; 489#if TC_SCMI_PD_CTRL_EN 490 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 491 scmi-perf-domain = <3>; 492#endif /* TC_SCMI_PD_CTRL_EN */ 493 494 pbha { 495 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 496 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 497 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 498 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 499 <22 0x32>, <24 0x22>, <28 0x32>; 500 propagate-bits = <0x0f>; 501 }; 502 }; 503 504 power_model_simple { 505 /* 506 * Numbers used are irrelevant to Titan, 507 * it helps suppressing the kernel warnings. 508 */ 509 compatible = "arm,mali-simple-power-model"; 510 static-coefficient = <2427750>; 511 dynamic-coefficient = <4687>; 512 ts = <20000 2000 (-20) 2>; 513 thermal-zone = ""; 514 }; 515 516 smmu_600: smmu@2ce00000 { 517 compatible = "arm,smmu-v3"; 518 reg = <0 0x2ce00000 0 0x20000>; 519 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>, 520 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>, 521 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>, 522 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>; 523 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; 524 #iommu-cells = <1>; 525 status = "disabled"; 526 }; 527 528 smmu_700: iommu@3f000000 { 529 #iommu-cells = <1>; 530 compatible = "arm,smmu-v3"; 531 reg = <0x0 0x3f000000 0x0 0x5000000>; 532 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>, 533 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>, 534 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>; 535 interrupt-names = "eventq", "cmdq-sync", "gerror"; 536 dma-coherent; 537 status = "disabled"; 538 }; 539 540 smmu_700_dpu: iommu@4002a00000 { 541 #iommu-cells = <1>; 542 compatible = "arm,smmu-v3"; 543 reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>; 544 interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>, 545 <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>, 546 <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>; 547 interrupt-names = "eventq", "cmdq-sync", "gerror"; 548 dma-coherent; 549 status = "disabled"; 550 }; 551 552 dp0: display@DPU_ADDR { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 compatible = "arm,mali-d71"; 556 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 557 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>; 558 interrupt-names = "DPU"; 559 DPU_CLK_ATTR1; 560 561 pl0: pipeline@0 { 562 reg = <0>; 563 DPU_CLK_ATTR2; 564 pl_id = <0>; 565 ports { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 port@0 { 569 reg = <0>; 570 dp_pl0_out0: endpoint { 571 remote-endpoint = <&lcd_in>; 572 }; 573 }; 574 }; 575 }; 576 577 pl1: pipeline@1 { 578 reg = <1>; 579 DPU_CLK_ATTR3; 580 pl_id = <1>; 581 ports { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 port@0 { 585 reg = <0>; 586 }; 587 }; 588 }; 589 }; 590 591 /* 592 * L3 cache in the DSU is the Memory System Component (MSC) 593 * The MPAM registers are accessed through utility bus in the DSU 594 */ 595 dsu-msc0 { 596 compatible = "arm,mpam-msc"; 597 reg = <DSU_MPAM_ADDR 0x0 0x2000>; 598 }; 599 600 ete0 { 601 compatible = "arm,embedded-trace-extension"; 602 cpu = <&CPU0>; 603 }; 604 605 ete1 { 606 compatible = "arm,embedded-trace-extension"; 607 cpu = <&CPU1>; 608 }; 609 610 ete2 { 611 compatible = "arm,embedded-trace-extension"; 612 cpu = <&CPU2>; 613 }; 614 615 ete3 { 616 compatible = "arm,embedded-trace-extension"; 617 cpu = <&CPU3>; 618 }; 619 620 ete4 { 621 compatible = "arm,embedded-trace-extension"; 622 cpu = <&CPU4>; 623 }; 624 625 ete5 { 626 compatible = "arm,embedded-trace-extension"; 627 cpu = <&CPU5>; 628 }; 629 630 ete6 { 631 compatible = "arm,embedded-trace-extension"; 632 cpu = <&CPU6>; 633 }; 634 635 ete7 { 636 compatible = "arm,embedded-trace-extension"; 637 cpu = <&CPU7>; 638 }; 639 640 trbe { 641 compatible = "arm,trace-buffer-extension"; 642 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>; 643 }; 644 645 trusty { 646 #size-cells = <0x02>; 647 #address-cells = <0x02>; 648 ranges = <0x00>; 649 compatible = "android,trusty-v1"; 650 651 virtio { 652 compatible = "android,trusty-virtio-v1"; 653 }; 654 655 test { 656 compatible = "android,trusty-test-v1"; 657 }; 658 659 log { 660 compatible = "android,trusty-log-v1"; 661 }; 662 663 irq { 664 ipi-range = <0x08 0x0f 0x08>; 665 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 666 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 667 compatible = "android,trusty-irq-v1"; 668 }; 669 }; 670 671 /* used in U-boot, Linux doesn't care */ 672 arm_ffa { 673 compatible = "arm,ffa"; 674 method = "smc"; 675 }; 676}; 677