1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 195 if (is_feat_fgt2_supported()) { 196 fgt2_enable(ctx); 197 } 198 199 if (is_feat_debugv8p9_supported()) { 200 debugv8p9_extended_bp_wp_enable(ctx); 201 } 202 203 if (is_feat_brbe_supported()) { 204 brbe_enable(ctx); 205 } 206 207 } 208 #endif /* ENABLE_RME */ 209 210 /****************************************************************************** 211 * This function performs initializations that are specific to NON-SECURE state 212 * and updates the cpu context specified by 'ctx'. 213 *****************************************************************************/ 214 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 215 { 216 u_register_t scr_el3; 217 el3_state_t *state; 218 219 state = get_el3state_ctx(ctx); 220 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 221 222 /* SCR_NS: Set the NS bit */ 223 scr_el3 |= SCR_NS_BIT; 224 225 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 226 if (is_feat_mte2_supported()) { 227 scr_el3 |= SCR_ATA_BIT; 228 } 229 230 #if !CTX_INCLUDE_PAUTH_REGS 231 /* 232 * Pointer Authentication feature, if present, is always enabled by default 233 * for Non secure lower exception levels. We do not have an explicit 234 * flag to set it. 235 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 236 * exception levels of secure and realm worlds. 237 * 238 * To prevent the leakage between the worlds during world switch, 239 * we enable it only for the non-secure world. 240 * 241 * If the Secure/realm world wants to use pointer authentication, 242 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 243 * it will be enabled globally for all the contexts. 244 * 245 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 246 * other than EL3 247 * 248 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 249 * than EL3 250 */ 251 if (is_armv8_3_pauth_present()) { 252 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 253 } 254 #endif /* CTX_INCLUDE_PAUTH_REGS */ 255 256 #if HANDLE_EA_EL3_FIRST_NS 257 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 258 scr_el3 |= SCR_EA_BIT; 259 #endif 260 261 #if RAS_TRAP_NS_ERR_REC_ACCESS 262 /* 263 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 264 * and RAS ERX registers from EL1 and EL2(from any security state) 265 * are trapped to EL3. 266 * Set here to trap only for NS EL1/EL2 267 */ 268 scr_el3 |= SCR_TERR_BIT; 269 #endif 270 271 /* CSV2 version 2 and above */ 272 if (is_feat_csv2_2_supported()) { 273 /* Enable access to the SCXTNUM_ELx registers. */ 274 scr_el3 |= SCR_EnSCXT_BIT; 275 } 276 277 #ifdef IMAGE_BL31 278 /* 279 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 280 * indicated by the interrupt routing model for BL31. 281 */ 282 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 283 #endif 284 285 if (is_feat_the_supported()) { 286 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 287 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 288 */ 289 scr_el3 |= SCR_RCWMASKEn_BIT; 290 } 291 292 if (is_feat_sctlr2_supported()) { 293 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 294 * SCTLR2_ELx registers. 295 */ 296 scr_el3 |= SCR_SCTLR2En_BIT; 297 } 298 299 if (is_feat_d128_supported()) { 300 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 301 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 302 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 303 */ 304 scr_el3 |= SCR_D128En_BIT; 305 } 306 307 if (is_feat_fpmr_supported()) { 308 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 309 * register. 310 */ 311 scr_el3 |= SCR_EnFPM_BIT; 312 } 313 314 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 315 316 /* Initialize EL2 context registers */ 317 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 318 319 /* 320 * Initialize SCTLR_EL2 context register with reset value. 321 */ 322 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 323 324 if (is_feat_hcx_supported()) { 325 /* 326 * Initialize register HCRX_EL2 with its init value. 327 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 328 * chance that this can lead to unexpected behavior in lower 329 * ELs that have not been updated since the introduction of 330 * this feature if not properly initialized, especially when 331 * it comes to those bits that enable/disable traps. 332 */ 333 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 334 HCRX_EL2_INIT_VAL); 335 } 336 337 if (is_feat_fgt_supported()) { 338 /* 339 * Initialize HFG*_EL2 registers with a default value so legacy 340 * systems unaware of FEAT_FGT do not get trapped due to their lack 341 * of initialization for this feature. 342 */ 343 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 344 HFGITR_EL2_INIT_VAL); 345 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 346 HFGRTR_EL2_INIT_VAL); 347 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 348 HFGWTR_EL2_INIT_VAL); 349 } 350 #else 351 /* Initialize EL1 context registers */ 352 setup_el1_context(ctx, ep); 353 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 354 355 manage_extensions_nonsecure(ctx); 356 } 357 358 /******************************************************************************* 359 * The following function performs initialization of the cpu_context 'ctx' 360 * for first use that is common to all security states, and sets the 361 * initial entrypoint state as specified by the entry_point_info structure. 362 * 363 * The EE and ST attributes are used to configure the endianness and secure 364 * timer availability for the new execution context. 365 ******************************************************************************/ 366 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 367 { 368 u_register_t scr_el3; 369 u_register_t mdcr_el3; 370 el3_state_t *state; 371 gp_regs_t *gp_regs; 372 373 state = get_el3state_ctx(ctx); 374 375 /* Clear any residual register values from the context */ 376 zeromem(ctx, sizeof(*ctx)); 377 378 /* 379 * The lower-EL context is zeroed so that no stale values leak to a world. 380 * It is assumed that an all-zero lower-EL context is good enough for it 381 * to boot correctly. However, there are very few registers where this 382 * is not true and some values need to be recreated. 383 */ 384 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 385 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 386 387 /* 388 * These bits are set in the gicv3 driver. Losing them (especially the 389 * SRE bit) is problematic for all worlds. Henceforth recreate them. 390 */ 391 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 392 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 393 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 394 395 /* 396 * The actlr_el2 register can be initialized in platform's reset handler 397 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 398 */ 399 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 400 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 401 402 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 403 scr_el3 = SCR_RESET_VAL; 404 405 /* 406 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 407 * EL2, EL1 and EL0 are not trapped to EL3. 408 * 409 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 410 * EL2, EL1 and EL0 are not trapped to EL3. 411 * 412 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 413 * both Security states and both Execution states. 414 * 415 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 416 * Non-secure memory. 417 */ 418 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 419 420 scr_el3 |= SCR_SIF_BIT; 421 422 /* 423 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 424 * Exception level as specified by SPSR. 425 */ 426 if (GET_RW(ep->spsr) == MODE_RW_64) { 427 scr_el3 |= SCR_RW_BIT; 428 } 429 430 /* 431 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 432 * Secure timer registers to EL3, from AArch64 state only, if specified 433 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 434 * bit always behaves as 1 (i.e. secure physical timer register access 435 * is not trapped) 436 */ 437 if (EP_GET_ST(ep->h.attr) != 0U) { 438 scr_el3 |= SCR_ST_BIT; 439 } 440 441 /* 442 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 443 * SCR_EL3.HXEn. 444 */ 445 if (is_feat_hcx_supported()) { 446 scr_el3 |= SCR_HXEn_BIT; 447 } 448 449 /* 450 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 451 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 452 * SCR_EL3.EnAS0. 453 */ 454 if (is_feat_ls64_accdata_supported()) { 455 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 456 } 457 458 /* 459 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 460 * registers are trapped to EL3. 461 */ 462 if (is_feat_rng_trap_supported()) { 463 scr_el3 |= SCR_TRNDR_BIT; 464 } 465 466 #if FAULT_INJECTION_SUPPORT 467 /* Enable fault injection from lower ELs */ 468 scr_el3 |= SCR_FIEN_BIT; 469 #endif 470 471 #if CTX_INCLUDE_PAUTH_REGS 472 /* 473 * Enable Pointer Authentication globally for all the worlds. 474 * 475 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 476 * other than EL3 477 * 478 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 479 * than EL3 480 */ 481 if (is_armv8_3_pauth_present()) { 482 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 483 } 484 #endif /* CTX_INCLUDE_PAUTH_REGS */ 485 486 /* 487 * SCR_EL3.PIEN: Enable permission indirection and overlay 488 * registers for AArch64 if present. 489 */ 490 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 491 scr_el3 |= SCR_PIEN_BIT; 492 } 493 494 /* 495 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 496 */ 497 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 498 scr_el3 |= SCR_GCSEn_BIT; 499 } 500 501 /* 502 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 503 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 504 * next mode is Hyp. 505 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 506 * same conditions as HVC instructions and when the processor supports 507 * ARMv8.6-FGT. 508 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 509 * CNTPOFF_EL2 register under the same conditions as HVC instructions 510 * and when the processor supports ECV. 511 */ 512 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 513 || ((GET_RW(ep->spsr) != MODE_RW_64) 514 && (GET_M32(ep->spsr) == MODE32_hyp))) { 515 scr_el3 |= SCR_HCE_BIT; 516 517 if (is_feat_fgt_supported()) { 518 scr_el3 |= SCR_FGTEN_BIT; 519 } 520 521 if (is_feat_ecv_supported()) { 522 scr_el3 |= SCR_ECVEN_BIT; 523 } 524 } 525 526 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 527 if (is_feat_twed_supported()) { 528 /* Set delay in SCR_EL3 */ 529 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 530 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 531 << SCR_TWEDEL_SHIFT); 532 533 /* Enable WFE delay */ 534 scr_el3 |= SCR_TWEDEn_BIT; 535 } 536 537 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 538 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 539 if (is_feat_sel2_supported()) { 540 scr_el3 |= SCR_EEL2_BIT; 541 } 542 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 543 544 if (is_feat_mec_supported()) { 545 scr_el3 |= SCR_MECEn_BIT; 546 } 547 548 /* 549 * Populate EL3 state so that we've the right context 550 * before doing ERET 551 */ 552 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 553 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 554 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 555 556 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 557 mdcr_el3 = MDCR_EL3_RESET_VAL; 558 559 /* --------------------------------------------------------------------- 560 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 561 * Some fields are architecturally UNKNOWN on reset. 562 * 563 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 564 * Debug exceptions, other than Breakpoint Instruction exceptions, are 565 * disabled from all ELs in Secure state. 566 * 567 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 568 * privileged debug from S-EL1. 569 * 570 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 571 * access to the powerdown debug registers do not trap to EL3. 572 * 573 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 574 * debug registers, other than those registers that are controlled by 575 * MDCR_EL3.TDOSA. 576 */ 577 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 578 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 579 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 580 581 #if IMAGE_BL31 582 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 583 if (is_feat_trf_supported()) { 584 trf_enable(ctx); 585 } 586 587 if (is_feat_tcr2_supported()) { 588 tcr2_enable(ctx); 589 } 590 591 pmuv3_enable(ctx); 592 #endif /* IMAGE_BL31 */ 593 594 /* 595 * Store the X0-X7 value from the entrypoint into the context 596 * Use memcpy as we are in control of the layout of the structures 597 */ 598 gp_regs = get_gpregs_ctx(ctx); 599 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 600 } 601 602 /******************************************************************************* 603 * Context management library initialization routine. This library is used by 604 * runtime services to share pointers to 'cpu_context' structures for secure 605 * non-secure and realm states. Management of the structures and their associated 606 * memory is not done by the context management library e.g. the PSCI service 607 * manages the cpu context used for entry from and exit to the non-secure state. 608 * The Secure payload dispatcher service manages the context(s) corresponding to 609 * the secure state. It also uses this library to get access to the non-secure 610 * state cpu context pointers. 611 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 612 * which will be used for programming an entry into a lower EL. The same context 613 * will be used to save state upon exception entry from that EL. 614 ******************************************************************************/ 615 void __init cm_init(void) 616 { 617 /* 618 * The context management library has only global data to initialize, but 619 * that will be done when the BSS is zeroed out. 620 */ 621 } 622 623 /******************************************************************************* 624 * This is the high-level function used to initialize the cpu_context 'ctx' for 625 * first use. It performs initializations that are common to all security states 626 * and initializations specific to the security state specified in 'ep' 627 ******************************************************************************/ 628 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 629 { 630 unsigned int security_state; 631 632 assert(ctx != NULL); 633 634 /* 635 * Perform initializations that are common 636 * to all security states 637 */ 638 setup_context_common(ctx, ep); 639 640 security_state = GET_SECURITY_STATE(ep->h.attr); 641 642 /* Perform security state specific initializations */ 643 switch (security_state) { 644 case SECURE: 645 setup_secure_context(ctx, ep); 646 break; 647 #if ENABLE_RME 648 case REALM: 649 setup_realm_context(ctx, ep); 650 break; 651 #endif 652 case NON_SECURE: 653 setup_ns_context(ctx, ep); 654 break; 655 default: 656 ERROR("Invalid security state\n"); 657 panic(); 658 break; 659 } 660 } 661 662 /******************************************************************************* 663 * Enable architecture extensions for EL3 execution. This function only updates 664 * registers in-place which are expected to either never change or be 665 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 666 ******************************************************************************/ 667 #if IMAGE_BL31 668 void cm_manage_extensions_el3(unsigned int my_idx) 669 { 670 if (is_feat_sve_supported()) { 671 sve_init_el3(); 672 } 673 674 if (is_feat_amu_supported()) { 675 amu_init_el3(my_idx); 676 } 677 678 if (is_feat_sme_supported()) { 679 sme_init_el3(); 680 } 681 682 pmuv3_init_el3(); 683 } 684 #endif /* IMAGE_BL31 */ 685 686 /****************************************************************************** 687 * Function to initialise the registers with the RESET values in the context 688 * memory, which are maintained per world. 689 ******************************************************************************/ 690 #if IMAGE_BL31 691 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 692 { 693 /* 694 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 695 * 696 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 697 * by Advanced SIMD, floating-point or SVE instructions (if 698 * implemented) do not trap to EL3. 699 * 700 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 701 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 702 */ 703 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 704 705 per_world_ctx->ctx_cptr_el3 = cptr_el3; 706 707 /* 708 * Initialize MPAM3_EL3 to its default reset value 709 * 710 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 711 * all lower ELn MPAM3_EL3 register access to, trap to EL3 712 */ 713 714 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 715 } 716 #endif /* IMAGE_BL31 */ 717 718 /******************************************************************************* 719 * Initialise per_world_context for Non-Secure world. 720 * This function enables the architecture extensions, which have same value 721 * across the cores for the non-secure world. 722 ******************************************************************************/ 723 #if IMAGE_BL31 724 void manage_extensions_nonsecure_per_world(void) 725 { 726 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 727 728 if (is_feat_sme_supported()) { 729 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 730 } 731 732 if (is_feat_sve_supported()) { 733 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 734 } 735 736 if (is_feat_amu_supported()) { 737 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 738 } 739 740 if (is_feat_sys_reg_trace_supported()) { 741 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 742 } 743 744 if (is_feat_mpam_supported()) { 745 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 746 } 747 748 if (is_feat_fpmr_supported()) { 749 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 750 } 751 } 752 #endif /* IMAGE_BL31 */ 753 754 /******************************************************************************* 755 * Initialise per_world_context for Secure world. 756 * This function enables the architecture extensions, which have same value 757 * across the cores for the secure world. 758 ******************************************************************************/ 759 static void manage_extensions_secure_per_world(void) 760 { 761 #if IMAGE_BL31 762 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 763 764 if (is_feat_sme_supported()) { 765 766 if (ENABLE_SME_FOR_SWD) { 767 /* 768 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 769 * SME, SVE, and FPU/SIMD context properly managed. 770 */ 771 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 772 } else { 773 /* 774 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 775 * world can safely use the associated registers. 776 */ 777 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 778 } 779 } 780 if (is_feat_sve_supported()) { 781 if (ENABLE_SVE_FOR_SWD) { 782 /* 783 * Enable SVE and FPU in secure context, SPM must ensure 784 * that the SVE and FPU register contexts are properly managed. 785 */ 786 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 787 } else { 788 /* 789 * Disable SVE and FPU in secure context so non-secure world 790 * can safely use them. 791 */ 792 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 793 } 794 } 795 796 /* NS can access this but Secure shouldn't */ 797 if (is_feat_sys_reg_trace_supported()) { 798 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 799 } 800 801 has_secure_perworld_init = true; 802 #endif /* IMAGE_BL31 */ 803 } 804 805 /******************************************************************************* 806 * Enable architecture extensions on first entry to Non-secure world. 807 ******************************************************************************/ 808 static void manage_extensions_nonsecure(cpu_context_t *ctx) 809 { 810 #if IMAGE_BL31 811 /* NOTE: registers are not context switched */ 812 if (is_feat_amu_supported()) { 813 amu_enable(ctx); 814 } 815 816 if (is_feat_sme_supported()) { 817 sme_enable(ctx); 818 } 819 820 if (is_feat_fgt2_supported()) { 821 fgt2_enable(ctx); 822 } 823 824 if (is_feat_debugv8p9_supported()) { 825 debugv8p9_extended_bp_wp_enable(ctx); 826 } 827 828 /* 829 * SPE, TRBE, and BRBE have multi-field enables that affect which world 830 * they apply to. Despite this, it is useful to ignore these for 831 * simplicity in determining the feature's per world enablement status. 832 * This is only possible when context is written per-world. Relied on 833 * by SMCCC_ARCH_FEATURE_AVAILABILITY 834 */ 835 if (is_feat_spe_supported()) { 836 spe_enable(ctx); 837 } 838 839 if (!check_if_trbe_disable_affected_core()) { 840 if (is_feat_trbe_supported()) { 841 trbe_enable(ctx); 842 } 843 } 844 845 if (is_feat_brbe_supported()) { 846 brbe_enable(ctx); 847 } 848 #endif /* IMAGE_BL31 */ 849 } 850 851 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 852 static __unused void enable_pauth_el2(void) 853 { 854 u_register_t hcr_el2 = read_hcr_el2(); 855 /* 856 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 857 * accessing key registers or using pointer authentication instructions 858 * from lower ELs. 859 */ 860 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 861 862 write_hcr_el2(hcr_el2); 863 } 864 865 #if INIT_UNUSED_NS_EL2 866 /******************************************************************************* 867 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 868 * world when EL2 is empty and unused. 869 ******************************************************************************/ 870 static void manage_extensions_nonsecure_el2_unused(void) 871 { 872 #if IMAGE_BL31 873 if (is_feat_spe_supported()) { 874 spe_init_el2_unused(); 875 } 876 877 if (is_feat_amu_supported()) { 878 amu_init_el2_unused(); 879 } 880 881 if (is_feat_mpam_supported()) { 882 mpam_init_el2_unused(); 883 } 884 885 if (is_feat_trbe_supported()) { 886 trbe_init_el2_unused(); 887 } 888 889 if (is_feat_sys_reg_trace_supported()) { 890 sys_reg_trace_init_el2_unused(); 891 } 892 893 if (is_feat_trf_supported()) { 894 trf_init_el2_unused(); 895 } 896 897 pmuv3_init_el2_unused(); 898 899 if (is_feat_sve_supported()) { 900 sve_init_el2_unused(); 901 } 902 903 if (is_feat_sme_supported()) { 904 sme_init_el2_unused(); 905 } 906 907 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 908 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 909 } 910 911 #if ENABLE_PAUTH 912 enable_pauth_el2(); 913 #endif /* ENABLE_PAUTH */ 914 #endif /* IMAGE_BL31 */ 915 } 916 #endif /* INIT_UNUSED_NS_EL2 */ 917 918 /******************************************************************************* 919 * Enable architecture extensions on first entry to Secure world. 920 ******************************************************************************/ 921 static void manage_extensions_secure(cpu_context_t *ctx) 922 { 923 #if IMAGE_BL31 924 if (is_feat_sme_supported()) { 925 if (ENABLE_SME_FOR_SWD) { 926 /* 927 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 928 * must ensure SME, SVE, and FPU/SIMD context properly managed. 929 */ 930 sme_init_el3(); 931 sme_enable(ctx); 932 } else { 933 /* 934 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 935 * world can safely use the associated registers. 936 */ 937 sme_disable(ctx); 938 } 939 } 940 941 /* 942 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 943 * sysreg access can. In case the EL1 controls leave them active on 944 * context switch, we want the owning security state to be NS so Secure 945 * can't be DOSed. 946 */ 947 if (is_feat_spe_supported()) { 948 spe_disable(ctx); 949 } 950 951 if (is_feat_trbe_supported()) { 952 trbe_disable(ctx); 953 } 954 #endif /* IMAGE_BL31 */ 955 } 956 957 /******************************************************************************* 958 * The following function initializes the cpu_context for the current CPU 959 * for first use, and sets the initial entrypoint state as specified by the 960 * entry_point_info structure. 961 ******************************************************************************/ 962 void cm_init_my_context(const entry_point_info_t *ep) 963 { 964 cpu_context_t *ctx; 965 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 966 cm_setup_context(ctx, ep); 967 } 968 969 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 970 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 971 { 972 #if INIT_UNUSED_NS_EL2 973 u_register_t hcr_el2 = HCR_RESET_VAL; 974 u_register_t mdcr_el2; 975 u_register_t scr_el3; 976 977 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 978 979 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 980 if ((scr_el3 & SCR_RW_BIT) != 0U) { 981 hcr_el2 |= HCR_RW_BIT; 982 } 983 984 write_hcr_el2(hcr_el2); 985 986 /* 987 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 988 * All fields have architecturally UNKNOWN reset values. 989 */ 990 write_cptr_el2(CPTR_EL2_RESET_VAL); 991 992 /* 993 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 994 * reset and are set to zero except for field(s) listed below. 995 * 996 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 997 * Non-secure EL0 and EL1 accesses to the physical timer registers. 998 * 999 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1000 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1001 */ 1002 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1003 1004 /* 1005 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1006 * UNKNOWN value. 1007 */ 1008 write_cntvoff_el2(0); 1009 1010 /* 1011 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1012 * respectively. 1013 */ 1014 write_vpidr_el2(read_midr_el1()); 1015 write_vmpidr_el2(read_mpidr_el1()); 1016 1017 /* 1018 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1019 * 1020 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1021 * translation is disabled, cache maintenance operations depend on the 1022 * VMID. 1023 * 1024 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1025 * disabled. 1026 */ 1027 write_vttbr_el2(VTTBR_RESET_VAL & 1028 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1029 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1030 1031 /* 1032 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1033 * Some fields are architecturally UNKNOWN on reset. 1034 * 1035 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1036 * register accesses to the Debug ROM registers are not trapped to EL2. 1037 * 1038 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1039 * accesses to the powerdown debug registers are not trapped to EL2. 1040 * 1041 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1042 * debug registers do not trap to EL2. 1043 * 1044 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1045 * EL2. 1046 */ 1047 mdcr_el2 = MDCR_EL2_RESET_VAL & 1048 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1049 MDCR_EL2_TDE_BIT); 1050 1051 write_mdcr_el2(mdcr_el2); 1052 1053 /* 1054 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1055 * 1056 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1057 * EL1 accesses to System registers do not trap to EL2. 1058 */ 1059 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1060 1061 /* 1062 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1063 * reset. 1064 * 1065 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1066 * and prevent timer interrupts. 1067 */ 1068 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1069 1070 manage_extensions_nonsecure_el2_unused(); 1071 #endif /* INIT_UNUSED_NS_EL2 */ 1072 } 1073 1074 /******************************************************************************* 1075 * Prepare the CPU system registers for first entry into realm, secure, or 1076 * normal world. 1077 * 1078 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1079 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1080 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1081 * For all entries, the EL1 registers are initialized from the cpu_context 1082 ******************************************************************************/ 1083 void cm_prepare_el3_exit(uint32_t security_state) 1084 { 1085 u_register_t sctlr_el2, scr_el3; 1086 cpu_context_t *ctx = cm_get_context(security_state); 1087 1088 assert(ctx != NULL); 1089 1090 if (security_state == NON_SECURE) { 1091 uint64_t el2_implemented = el_implemented(2); 1092 1093 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1094 CTX_SCR_EL3); 1095 1096 if (el2_implemented != EL_IMPL_NONE) { 1097 1098 /* 1099 * If context is not being used for EL2, initialize 1100 * HCRX_EL2 with its init value here. 1101 */ 1102 if (is_feat_hcx_supported()) { 1103 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1104 } 1105 1106 /* 1107 * Initialize Fine-grained trap registers introduced 1108 * by FEAT_FGT so all traps are initially disabled when 1109 * switching to EL2 or a lower EL, preventing undesired 1110 * behavior. 1111 */ 1112 if (is_feat_fgt_supported()) { 1113 /* 1114 * Initialize HFG*_EL2 registers with a default 1115 * value so legacy systems unaware of FEAT_FGT 1116 * do not get trapped due to their lack of 1117 * initialization for this feature. 1118 */ 1119 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1120 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1121 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1122 } 1123 1124 /* Condition to ensure EL2 is being used. */ 1125 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1126 /* Initialize SCTLR_EL2 register with reset value. */ 1127 sctlr_el2 = SCTLR_EL2_RES1; 1128 1129 /* 1130 * If workaround of errata 764081 for Cortex-A75 1131 * is used then set SCTLR_EL2.IESB to enable 1132 * Implicit Error Synchronization Barrier. 1133 */ 1134 if (errata_a75_764081_applies()) { 1135 sctlr_el2 |= SCTLR_IESB_BIT; 1136 } 1137 1138 write_sctlr_el2(sctlr_el2); 1139 } else { 1140 /* 1141 * (scr_el3 & SCR_HCE_BIT==0) 1142 * EL2 implemented but unused. 1143 */ 1144 init_nonsecure_el2_unused(ctx); 1145 } 1146 } 1147 } 1148 #if (!CTX_INCLUDE_EL2_REGS) 1149 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1150 cm_el1_sysregs_context_restore(security_state); 1151 #endif 1152 cm_set_next_eret_context(security_state); 1153 } 1154 1155 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1156 1157 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1158 { 1159 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1160 if (is_feat_amu_supported()) { 1161 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1162 } 1163 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1164 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1165 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1166 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1167 } 1168 1169 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1170 { 1171 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1172 if (is_feat_amu_supported()) { 1173 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1174 } 1175 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1176 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1177 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1178 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1179 } 1180 1181 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1182 { 1183 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1184 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1185 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1186 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1187 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1188 } 1189 1190 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1191 { 1192 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1193 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1194 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1195 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1196 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1197 } 1198 1199 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1200 { 1201 u_register_t mpam_idr = read_mpamidr_el1(); 1202 1203 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1204 1205 /* 1206 * The context registers that we intend to save would be part of the 1207 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1208 */ 1209 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1210 return; 1211 } 1212 1213 /* 1214 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1215 * MPAMIDR_HAS_HCR_BIT == 1. 1216 */ 1217 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1218 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1219 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1220 1221 /* 1222 * The number of MPAMVPM registers is implementation defined, their 1223 * number is stored in the MPAMIDR_EL1 register. 1224 */ 1225 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1226 case 7: 1227 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1228 __fallthrough; 1229 case 6: 1230 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1231 __fallthrough; 1232 case 5: 1233 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1234 __fallthrough; 1235 case 4: 1236 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1237 __fallthrough; 1238 case 3: 1239 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1240 __fallthrough; 1241 case 2: 1242 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1243 __fallthrough; 1244 case 1: 1245 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1246 break; 1247 } 1248 } 1249 1250 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1251 { 1252 u_register_t mpam_idr = read_mpamidr_el1(); 1253 1254 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1255 1256 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1257 return; 1258 } 1259 1260 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1261 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1262 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1263 1264 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1265 case 7: 1266 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1267 __fallthrough; 1268 case 6: 1269 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1270 __fallthrough; 1271 case 5: 1272 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1273 __fallthrough; 1274 case 4: 1275 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1276 __fallthrough; 1277 case 3: 1278 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1279 __fallthrough; 1280 case 2: 1281 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1282 __fallthrough; 1283 case 1: 1284 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1285 break; 1286 } 1287 } 1288 1289 /* --------------------------------------------------------------------------- 1290 * The following registers are not added: 1291 * ICH_AP0R<n>_EL2 1292 * ICH_AP1R<n>_EL2 1293 * ICH_LR<n>_EL2 1294 * 1295 * NOTE: For a system with S-EL2 present but not enabled, accessing 1296 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1297 * SCR_EL3.NS = 1 before accessing this register. 1298 * --------------------------------------------------------------------------- 1299 */ 1300 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1301 { 1302 u_register_t scr_el3 = read_scr_el3(); 1303 1304 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1305 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1306 #else 1307 write_scr_el3(scr_el3 | SCR_NS_BIT); 1308 isb(); 1309 1310 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1311 1312 write_scr_el3(scr_el3); 1313 isb(); 1314 #endif 1315 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1316 1317 if (errata_ich_vmcr_el2_applies()) { 1318 if (security_state == SECURE) { 1319 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1320 } else { 1321 write_scr_el3(scr_el3 | SCR_NS_BIT); 1322 } 1323 isb(); 1324 } 1325 1326 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1327 1328 if (errata_ich_vmcr_el2_applies()) { 1329 write_scr_el3(scr_el3); 1330 isb(); 1331 } 1332 } 1333 1334 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1335 { 1336 u_register_t scr_el3 = read_scr_el3(); 1337 1338 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1339 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1340 #else 1341 write_scr_el3(scr_el3 | SCR_NS_BIT); 1342 isb(); 1343 1344 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1345 1346 write_scr_el3(scr_el3); 1347 isb(); 1348 #endif 1349 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1350 1351 if (errata_ich_vmcr_el2_applies()) { 1352 if (security_state == SECURE) { 1353 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1354 } else { 1355 write_scr_el3(scr_el3 | SCR_NS_BIT); 1356 } 1357 isb(); 1358 } 1359 1360 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1361 1362 if (errata_ich_vmcr_el2_applies()) { 1363 write_scr_el3(scr_el3); 1364 isb(); 1365 } 1366 } 1367 1368 /* ----------------------------------------------------- 1369 * The following registers are not added: 1370 * AMEVCNTVOFF0<n>_EL2 1371 * AMEVCNTVOFF1<n>_EL2 1372 * ----------------------------------------------------- 1373 */ 1374 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1375 { 1376 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1377 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1378 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1379 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1380 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1381 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1382 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1383 if (CTX_INCLUDE_AARCH32_REGS) { 1384 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1385 } 1386 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1387 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1388 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1389 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1390 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1391 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1392 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1393 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1394 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1395 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1396 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1397 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1398 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1399 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1400 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1401 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1402 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1403 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1404 1405 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1406 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1407 } 1408 1409 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1410 { 1411 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1412 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1413 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1414 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1415 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1416 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1417 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1418 if (CTX_INCLUDE_AARCH32_REGS) { 1419 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1420 } 1421 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1422 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1423 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1424 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1425 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1426 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1427 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1428 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1429 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1430 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1431 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1432 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1433 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1434 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1435 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1436 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1437 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1438 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1439 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1440 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1441 } 1442 1443 /******************************************************************************* 1444 * Save EL2 sysreg context 1445 ******************************************************************************/ 1446 void cm_el2_sysregs_context_save(uint32_t security_state) 1447 { 1448 cpu_context_t *ctx; 1449 el2_sysregs_t *el2_sysregs_ctx; 1450 1451 ctx = cm_get_context(security_state); 1452 assert(ctx != NULL); 1453 1454 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1455 1456 el2_sysregs_context_save_common(el2_sysregs_ctx); 1457 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1458 1459 if (is_feat_mte2_supported()) { 1460 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1461 } 1462 1463 if (is_feat_mpam_supported()) { 1464 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1465 } 1466 1467 if (is_feat_fgt_supported()) { 1468 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1469 } 1470 1471 if (is_feat_fgt2_supported()) { 1472 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1473 } 1474 1475 if (is_feat_ecv_v2_supported()) { 1476 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1477 } 1478 1479 if (is_feat_vhe_supported()) { 1480 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1481 read_contextidr_el2()); 1482 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1483 } 1484 1485 if (is_feat_ras_supported()) { 1486 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1487 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1488 } 1489 1490 if (is_feat_nv2_supported()) { 1491 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1492 } 1493 1494 if (is_feat_trf_supported()) { 1495 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1496 } 1497 1498 if (is_feat_csv2_2_supported()) { 1499 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1500 read_scxtnum_el2()); 1501 } 1502 1503 if (is_feat_hcx_supported()) { 1504 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1505 } 1506 1507 if (is_feat_tcr2_supported()) { 1508 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1509 } 1510 1511 if (is_feat_sxpie_supported()) { 1512 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1513 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1514 } 1515 1516 if (is_feat_sxpoe_supported()) { 1517 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1518 } 1519 1520 if (is_feat_brbe_supported()) { 1521 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1522 } 1523 1524 if (is_feat_s2pie_supported()) { 1525 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1526 } 1527 1528 if (is_feat_gcs_supported()) { 1529 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1530 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1531 } 1532 1533 if (is_feat_sctlr2_supported()) { 1534 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1535 } 1536 } 1537 1538 /******************************************************************************* 1539 * Restore EL2 sysreg context 1540 ******************************************************************************/ 1541 void cm_el2_sysregs_context_restore(uint32_t security_state) 1542 { 1543 cpu_context_t *ctx; 1544 el2_sysregs_t *el2_sysregs_ctx; 1545 1546 ctx = cm_get_context(security_state); 1547 assert(ctx != NULL); 1548 1549 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1550 1551 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1552 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1553 1554 if (is_feat_mte2_supported()) { 1555 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1556 } 1557 1558 if (is_feat_mpam_supported()) { 1559 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1560 } 1561 1562 if (is_feat_fgt_supported()) { 1563 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1564 } 1565 1566 if (is_feat_fgt2_supported()) { 1567 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1568 } 1569 1570 if (is_feat_ecv_v2_supported()) { 1571 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1572 } 1573 1574 if (is_feat_vhe_supported()) { 1575 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1576 contextidr_el2)); 1577 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1578 } 1579 1580 if (is_feat_ras_supported()) { 1581 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1582 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1583 } 1584 1585 if (is_feat_nv2_supported()) { 1586 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1587 } 1588 1589 if (is_feat_trf_supported()) { 1590 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1591 } 1592 1593 if (is_feat_csv2_2_supported()) { 1594 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1595 scxtnum_el2)); 1596 } 1597 1598 if (is_feat_hcx_supported()) { 1599 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1600 } 1601 1602 if (is_feat_tcr2_supported()) { 1603 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1604 } 1605 1606 if (is_feat_sxpie_supported()) { 1607 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1608 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1609 } 1610 1611 if (is_feat_sxpoe_supported()) { 1612 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1613 } 1614 1615 if (is_feat_s2pie_supported()) { 1616 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1617 } 1618 1619 if (is_feat_gcs_supported()) { 1620 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1621 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1622 } 1623 1624 if (is_feat_sctlr2_supported()) { 1625 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1626 } 1627 1628 if (is_feat_brbe_supported()) { 1629 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1630 } 1631 } 1632 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1633 1634 /******************************************************************************* 1635 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1636 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1637 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1638 * cm_prepare_el3_exit function. 1639 ******************************************************************************/ 1640 void cm_prepare_el3_exit_ns(void) 1641 { 1642 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1643 #if ENABLE_ASSERTIONS 1644 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1645 assert(ctx != NULL); 1646 1647 /* Assert that EL2 is used. */ 1648 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1649 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1650 (el_implemented(2U) != EL_IMPL_NONE)); 1651 #endif /* ENABLE_ASSERTIONS */ 1652 1653 /* Restore EL2 sysreg contexts */ 1654 cm_el2_sysregs_context_restore(NON_SECURE); 1655 cm_set_next_eret_context(NON_SECURE); 1656 #else 1657 cm_prepare_el3_exit(NON_SECURE); 1658 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1659 } 1660 1661 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1662 /******************************************************************************* 1663 * The next set of six functions are used by runtime services to save and restore 1664 * EL1 context on the 'cpu_context' structure for the specified security state. 1665 ******************************************************************************/ 1666 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1667 { 1668 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1669 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1670 1671 #if (!ERRATA_SPECULATIVE_AT) 1672 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1673 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1674 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1675 1676 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1677 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1678 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1679 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1680 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1681 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1682 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1683 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1684 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1685 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1686 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1687 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1688 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1689 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1690 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1691 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1692 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1693 1694 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1695 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1696 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1697 1698 if (CTX_INCLUDE_AARCH32_REGS) { 1699 /* Save Aarch32 registers */ 1700 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1701 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1702 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1703 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1704 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1705 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1706 } 1707 1708 if (NS_TIMER_SWITCH) { 1709 /* Save NS Timer registers */ 1710 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1711 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1712 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1713 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1714 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1715 } 1716 1717 if (is_feat_mte2_supported()) { 1718 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1719 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1720 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1721 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1722 } 1723 1724 if (is_feat_ras_supported()) { 1725 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1726 } 1727 1728 if (is_feat_s1pie_supported()) { 1729 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1730 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1731 } 1732 1733 if (is_feat_s1poe_supported()) { 1734 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1735 } 1736 1737 if (is_feat_s2poe_supported()) { 1738 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1739 } 1740 1741 if (is_feat_tcr2_supported()) { 1742 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1743 } 1744 1745 if (is_feat_trf_supported()) { 1746 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1747 } 1748 1749 if (is_feat_csv2_2_supported()) { 1750 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1751 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1752 } 1753 1754 if (is_feat_gcs_supported()) { 1755 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1756 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1757 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1758 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1759 } 1760 1761 if (is_feat_the_supported()) { 1762 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1763 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1764 } 1765 1766 if (is_feat_sctlr2_supported()) { 1767 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1768 } 1769 1770 if (is_feat_ls64_accdata_supported()) { 1771 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1772 } 1773 } 1774 1775 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1776 { 1777 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1778 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1779 1780 #if (!ERRATA_SPECULATIVE_AT) 1781 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1782 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1783 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1784 1785 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1786 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1787 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1788 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1789 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1790 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1791 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1792 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1793 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1794 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1795 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1796 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1797 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1798 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1799 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1800 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1801 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1802 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1803 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1804 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1805 1806 if (CTX_INCLUDE_AARCH32_REGS) { 1807 /* Restore Aarch32 registers */ 1808 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1809 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1810 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1811 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1812 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1813 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1814 } 1815 1816 if (NS_TIMER_SWITCH) { 1817 /* Restore NS Timer registers */ 1818 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1819 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1820 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1821 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1822 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1823 } 1824 1825 if (is_feat_mte2_supported()) { 1826 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1827 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1828 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1829 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1830 } 1831 1832 if (is_feat_ras_supported()) { 1833 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1834 } 1835 1836 if (is_feat_s1pie_supported()) { 1837 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1838 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1839 } 1840 1841 if (is_feat_s1poe_supported()) { 1842 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1843 } 1844 1845 if (is_feat_s2poe_supported()) { 1846 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1847 } 1848 1849 if (is_feat_tcr2_supported()) { 1850 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1851 } 1852 1853 if (is_feat_trf_supported()) { 1854 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1855 } 1856 1857 if (is_feat_csv2_2_supported()) { 1858 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1859 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1860 } 1861 1862 if (is_feat_gcs_supported()) { 1863 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1864 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1865 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1866 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1867 } 1868 1869 if (is_feat_the_supported()) { 1870 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1871 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1872 } 1873 1874 if (is_feat_sctlr2_supported()) { 1875 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1876 } 1877 1878 if (is_feat_ls64_accdata_supported()) { 1879 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1880 } 1881 } 1882 1883 /******************************************************************************* 1884 * The next couple of functions are used by runtime services to save and restore 1885 * EL1 context on the 'cpu_context' structure for the specified security state. 1886 ******************************************************************************/ 1887 void cm_el1_sysregs_context_save(uint32_t security_state) 1888 { 1889 cpu_context_t *ctx; 1890 1891 ctx = cm_get_context(security_state); 1892 assert(ctx != NULL); 1893 1894 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1895 1896 #if IMAGE_BL31 1897 if (security_state == SECURE) { 1898 PUBLISH_EVENT(cm_exited_secure_world); 1899 } else { 1900 PUBLISH_EVENT(cm_exited_normal_world); 1901 } 1902 #endif 1903 } 1904 1905 void cm_el1_sysregs_context_restore(uint32_t security_state) 1906 { 1907 cpu_context_t *ctx; 1908 1909 ctx = cm_get_context(security_state); 1910 assert(ctx != NULL); 1911 1912 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1913 1914 #if IMAGE_BL31 1915 if (security_state == SECURE) { 1916 PUBLISH_EVENT(cm_entering_secure_world); 1917 } else { 1918 PUBLISH_EVENT(cm_entering_normal_world); 1919 } 1920 #endif 1921 } 1922 1923 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1924 1925 /******************************************************************************* 1926 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1927 * given security state with the given entrypoint 1928 ******************************************************************************/ 1929 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1930 { 1931 cpu_context_t *ctx; 1932 el3_state_t *state; 1933 1934 ctx = cm_get_context(security_state); 1935 assert(ctx != NULL); 1936 1937 /* Populate EL3 state so that ERET jumps to the correct entry */ 1938 state = get_el3state_ctx(ctx); 1939 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1940 } 1941 1942 /******************************************************************************* 1943 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1944 * pertaining to the given security state 1945 ******************************************************************************/ 1946 void cm_set_elr_spsr_el3(uint32_t security_state, 1947 uintptr_t entrypoint, uint32_t spsr) 1948 { 1949 cpu_context_t *ctx; 1950 el3_state_t *state; 1951 1952 ctx = cm_get_context(security_state); 1953 assert(ctx != NULL); 1954 1955 /* Populate EL3 state so that ERET jumps to the correct entry */ 1956 state = get_el3state_ctx(ctx); 1957 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1958 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1959 } 1960 1961 /******************************************************************************* 1962 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1963 * pertaining to the given security state using the value and bit position 1964 * specified in the parameters. It preserves all other bits. 1965 ******************************************************************************/ 1966 void cm_write_scr_el3_bit(uint32_t security_state, 1967 uint32_t bit_pos, 1968 uint32_t value) 1969 { 1970 cpu_context_t *ctx; 1971 el3_state_t *state; 1972 u_register_t scr_el3; 1973 1974 ctx = cm_get_context(security_state); 1975 assert(ctx != NULL); 1976 1977 /* Ensure that the bit position is a valid one */ 1978 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1979 1980 /* Ensure that the 'value' is only a bit wide */ 1981 assert(value <= 1U); 1982 1983 /* 1984 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1985 * and set it to its new value. 1986 */ 1987 state = get_el3state_ctx(ctx); 1988 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1989 scr_el3 &= ~(1UL << bit_pos); 1990 scr_el3 |= (u_register_t)value << bit_pos; 1991 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1992 } 1993 1994 /******************************************************************************* 1995 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1996 * given security state. 1997 ******************************************************************************/ 1998 u_register_t cm_get_scr_el3(uint32_t security_state) 1999 { 2000 const cpu_context_t *ctx; 2001 const el3_state_t *state; 2002 2003 ctx = cm_get_context(security_state); 2004 assert(ctx != NULL); 2005 2006 /* Populate EL3 state so that ERET jumps to the correct entry */ 2007 state = get_el3state_ctx(ctx); 2008 return read_ctx_reg(state, CTX_SCR_EL3); 2009 } 2010 2011 /******************************************************************************* 2012 * This function is used to program the context that's used for exception 2013 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2014 * the required security state 2015 ******************************************************************************/ 2016 void cm_set_next_eret_context(uint32_t security_state) 2017 { 2018 cpu_context_t *ctx; 2019 2020 ctx = cm_get_context(security_state); 2021 assert(ctx != NULL); 2022 2023 cm_set_next_context(ctx); 2024 } 2025