1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 } 152 153 #if ENABLE_RME 154 /****************************************************************************** 155 * This function performs initializations that are specific to REALM state 156 * and updates the cpu context specified by 'ctx'. 157 *****************************************************************************/ 158 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 159 { 160 u_register_t scr_el3; 161 el3_state_t *state; 162 163 state = get_el3state_ctx(ctx); 164 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 165 166 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 167 168 /* CSV2 version 2 and above */ 169 if (is_feat_csv2_2_supported()) { 170 /* Enable access to the SCXTNUM_ELx registers. */ 171 scr_el3 |= SCR_EnSCXT_BIT; 172 } 173 174 if (is_feat_sctlr2_supported()) { 175 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 176 * SCTLR2_ELx registers. 177 */ 178 scr_el3 |= SCR_SCTLR2En_BIT; 179 } 180 181 if (is_feat_d128_supported()) { 182 /* 183 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 184 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 185 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 186 */ 187 scr_el3 |= SCR_D128En_BIT; 188 } 189 190 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 191 192 if (is_feat_fgt2_supported()) { 193 fgt2_enable(ctx); 194 } 195 196 if (is_feat_debugv8p9_supported()) { 197 debugv8p9_extended_bp_wp_enable(ctx); 198 } 199 200 if (is_feat_brbe_supported()) { 201 brbe_enable(ctx); 202 } 203 204 } 205 #endif /* ENABLE_RME */ 206 207 /****************************************************************************** 208 * This function performs initializations that are specific to NON-SECURE state 209 * and updates the cpu context specified by 'ctx'. 210 *****************************************************************************/ 211 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 212 { 213 u_register_t scr_el3; 214 el3_state_t *state; 215 216 state = get_el3state_ctx(ctx); 217 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 218 219 /* SCR_NS: Set the NS bit */ 220 scr_el3 |= SCR_NS_BIT; 221 222 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 223 if (is_feat_mte2_supported()) { 224 scr_el3 |= SCR_ATA_BIT; 225 } 226 227 /* 228 * Pointer Authentication feature, if present, is always enabled by 229 * default for Non secure lower exception levels. We do not have an 230 * explicit flag to set it. To prevent the leakage between the worlds 231 * during world switch, we enable it only for the non-secure world. 232 * 233 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 234 * exception levels of secure and realm worlds. 235 * 236 * If the Secure/realm world wants to use pointer authentication, 237 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 238 * it will be enabled globally for all the contexts. 239 * 240 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 241 * other than EL3 242 * 243 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 244 * than EL3 245 */ 246 if (!is_ctx_pauth_supported()) { 247 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 248 } 249 250 #if HANDLE_EA_EL3_FIRST_NS 251 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 252 scr_el3 |= SCR_EA_BIT; 253 #endif 254 255 #if RAS_TRAP_NS_ERR_REC_ACCESS 256 /* 257 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 258 * and RAS ERX registers from EL1 and EL2(from any security state) 259 * are trapped to EL3. 260 * Set here to trap only for NS EL1/EL2 261 */ 262 scr_el3 |= SCR_TERR_BIT; 263 #endif 264 265 /* CSV2 version 2 and above */ 266 if (is_feat_csv2_2_supported()) { 267 /* Enable access to the SCXTNUM_ELx registers. */ 268 scr_el3 |= SCR_EnSCXT_BIT; 269 } 270 271 #ifdef IMAGE_BL31 272 /* 273 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 274 * indicated by the interrupt routing model for BL31. 275 */ 276 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 277 #endif 278 279 if (is_feat_the_supported()) { 280 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 281 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 282 */ 283 scr_el3 |= SCR_RCWMASKEn_BIT; 284 } 285 286 if (is_feat_sctlr2_supported()) { 287 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 288 * SCTLR2_ELx registers. 289 */ 290 scr_el3 |= SCR_SCTLR2En_BIT; 291 } 292 293 if (is_feat_d128_supported()) { 294 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 295 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 296 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 297 */ 298 scr_el3 |= SCR_D128En_BIT; 299 } 300 301 if (is_feat_fpmr_supported()) { 302 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 303 * register. 304 */ 305 scr_el3 |= SCR_EnFPM_BIT; 306 } 307 308 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 309 310 /* Initialize EL2 context registers */ 311 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 312 313 /* 314 * Initialize SCTLR_EL2 context register with reset value. 315 */ 316 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 317 318 if (is_feat_hcx_supported()) { 319 /* 320 * Initialize register HCRX_EL2 with its init value. 321 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 322 * chance that this can lead to unexpected behavior in lower 323 * ELs that have not been updated since the introduction of 324 * this feature if not properly initialized, especially when 325 * it comes to those bits that enable/disable traps. 326 */ 327 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 328 HCRX_EL2_INIT_VAL); 329 } 330 331 if (is_feat_fgt_supported()) { 332 /* 333 * Initialize HFG*_EL2 registers with a default value so legacy 334 * systems unaware of FEAT_FGT do not get trapped due to their lack 335 * of initialization for this feature. 336 */ 337 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 338 HFGITR_EL2_INIT_VAL); 339 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 340 HFGRTR_EL2_INIT_VAL); 341 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 342 HFGWTR_EL2_INIT_VAL); 343 } 344 #else 345 /* Initialize EL1 context registers */ 346 setup_el1_context(ctx, ep); 347 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 348 349 manage_extensions_nonsecure(ctx); 350 } 351 352 /******************************************************************************* 353 * The following function performs initialization of the cpu_context 'ctx' 354 * for first use that is common to all security states, and sets the 355 * initial entrypoint state as specified by the entry_point_info structure. 356 * 357 * The EE and ST attributes are used to configure the endianness and secure 358 * timer availability for the new execution context. 359 ******************************************************************************/ 360 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 361 { 362 u_register_t scr_el3; 363 u_register_t mdcr_el3; 364 el3_state_t *state; 365 gp_regs_t *gp_regs; 366 367 state = get_el3state_ctx(ctx); 368 369 /* Clear any residual register values from the context */ 370 zeromem(ctx, sizeof(*ctx)); 371 372 /* 373 * The lower-EL context is zeroed so that no stale values leak to a world. 374 * It is assumed that an all-zero lower-EL context is good enough for it 375 * to boot correctly. However, there are very few registers where this 376 * is not true and some values need to be recreated. 377 */ 378 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 379 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 380 381 /* 382 * These bits are set in the gicv3 driver. Losing them (especially the 383 * SRE bit) is problematic for all worlds. Henceforth recreate them. 384 */ 385 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 386 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 387 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 388 389 /* 390 * The actlr_el2 register can be initialized in platform's reset handler 391 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 392 */ 393 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 394 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 395 396 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 397 scr_el3 = SCR_RESET_VAL; 398 399 /* 400 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 401 * EL2, EL1 and EL0 are not trapped to EL3. 402 * 403 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 404 * EL2, EL1 and EL0 are not trapped to EL3. 405 * 406 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 407 * both Security states and both Execution states. 408 * 409 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 410 * Non-secure memory. 411 */ 412 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 413 414 scr_el3 |= SCR_SIF_BIT; 415 416 /* 417 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 418 * Exception level as specified by SPSR. 419 */ 420 if (GET_RW(ep->spsr) == MODE_RW_64) { 421 scr_el3 |= SCR_RW_BIT; 422 } 423 424 /* 425 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 426 * Secure timer registers to EL3, from AArch64 state only, if specified 427 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 428 * bit always behaves as 1 (i.e. secure physical timer register access 429 * is not trapped) 430 */ 431 if (EP_GET_ST(ep->h.attr) != 0U) { 432 scr_el3 |= SCR_ST_BIT; 433 } 434 435 /* 436 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 437 * SCR_EL3.HXEn. 438 */ 439 if (is_feat_hcx_supported()) { 440 scr_el3 |= SCR_HXEn_BIT; 441 } 442 443 /* 444 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 445 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 446 * SCR_EL3.EnAS0. 447 */ 448 if (is_feat_ls64_accdata_supported()) { 449 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 450 } 451 452 /* 453 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 454 * registers are trapped to EL3. 455 */ 456 if (is_feat_rng_trap_supported()) { 457 scr_el3 |= SCR_TRNDR_BIT; 458 } 459 460 #if FAULT_INJECTION_SUPPORT 461 /* Enable fault injection from lower ELs */ 462 scr_el3 |= SCR_FIEN_BIT; 463 #endif 464 465 /* 466 * Enable Pointer Authentication globally for all the worlds. 467 * 468 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 469 * other than EL3 470 * 471 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 472 * than EL3 473 */ 474 if (is_ctx_pauth_supported()) { 475 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 476 } 477 478 /* 479 * SCR_EL3.PIEN: Enable permission indirection and overlay 480 * registers for AArch64 if present. 481 */ 482 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 483 scr_el3 |= SCR_PIEN_BIT; 484 } 485 486 /* 487 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 488 */ 489 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 490 scr_el3 |= SCR_GCSEn_BIT; 491 } 492 493 /* 494 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 495 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 496 * next mode is Hyp. 497 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 498 * same conditions as HVC instructions and when the processor supports 499 * ARMv8.6-FGT. 500 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 501 * CNTPOFF_EL2 register under the same conditions as HVC instructions 502 * and when the processor supports ECV. 503 */ 504 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 505 || ((GET_RW(ep->spsr) != MODE_RW_64) 506 && (GET_M32(ep->spsr) == MODE32_hyp))) { 507 scr_el3 |= SCR_HCE_BIT; 508 509 if (is_feat_fgt_supported()) { 510 scr_el3 |= SCR_FGTEN_BIT; 511 } 512 513 if (is_feat_ecv_supported()) { 514 scr_el3 |= SCR_ECVEN_BIT; 515 } 516 } 517 518 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 519 if (is_feat_twed_supported()) { 520 /* Set delay in SCR_EL3 */ 521 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 522 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 523 << SCR_TWEDEL_SHIFT); 524 525 /* Enable WFE delay */ 526 scr_el3 |= SCR_TWEDEn_BIT; 527 } 528 529 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 530 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 531 if (is_feat_sel2_supported()) { 532 scr_el3 |= SCR_EEL2_BIT; 533 } 534 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 535 536 if (is_feat_mec_supported()) { 537 scr_el3 |= SCR_MECEn_BIT; 538 } 539 540 /* 541 * Populate EL3 state so that we've the right context 542 * before doing ERET 543 */ 544 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 545 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 546 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 547 548 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 549 mdcr_el3 = MDCR_EL3_RESET_VAL; 550 551 /* --------------------------------------------------------------------- 552 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 553 * Some fields are architecturally UNKNOWN on reset. 554 * 555 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 556 * Debug exceptions, other than Breakpoint Instruction exceptions, are 557 * disabled from all ELs in Secure state. 558 * 559 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 560 * privileged debug from S-EL1. 561 * 562 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 563 * access to the powerdown debug registers do not trap to EL3. 564 * 565 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 566 * debug registers, other than those registers that are controlled by 567 * MDCR_EL3.TDOSA. 568 */ 569 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 570 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 571 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 572 573 #if IMAGE_BL31 574 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 575 if (is_feat_trf_supported()) { 576 trf_enable(ctx); 577 } 578 579 if (is_feat_tcr2_supported()) { 580 tcr2_enable(ctx); 581 } 582 583 pmuv3_enable(ctx); 584 #endif /* IMAGE_BL31 */ 585 586 /* 587 * Store the X0-X7 value from the entrypoint into the context 588 * Use memcpy as we are in control of the layout of the structures 589 */ 590 gp_regs = get_gpregs_ctx(ctx); 591 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 592 } 593 594 /******************************************************************************* 595 * Context management library initialization routine. This library is used by 596 * runtime services to share pointers to 'cpu_context' structures for secure 597 * non-secure and realm states. Management of the structures and their associated 598 * memory is not done by the context management library e.g. the PSCI service 599 * manages the cpu context used for entry from and exit to the non-secure state. 600 * The Secure payload dispatcher service manages the context(s) corresponding to 601 * the secure state. It also uses this library to get access to the non-secure 602 * state cpu context pointers. 603 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 604 * which will be used for programming an entry into a lower EL. The same context 605 * will be used to save state upon exception entry from that EL. 606 ******************************************************************************/ 607 void __init cm_init(void) 608 { 609 /* 610 * The context management library has only global data to initialize, but 611 * that will be done when the BSS is zeroed out. 612 */ 613 } 614 615 /******************************************************************************* 616 * This is the high-level function used to initialize the cpu_context 'ctx' for 617 * first use. It performs initializations that are common to all security states 618 * and initializations specific to the security state specified in 'ep' 619 ******************************************************************************/ 620 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 621 { 622 size_t security_state; 623 624 assert(ctx != NULL); 625 626 /* 627 * Perform initializations that are common 628 * to all security states 629 */ 630 setup_context_common(ctx, ep); 631 632 security_state = GET_SECURITY_STATE(ep->h.attr); 633 634 /* Perform security state specific initializations */ 635 switch (security_state) { 636 case SECURE: 637 setup_secure_context(ctx, ep); 638 break; 639 #if ENABLE_RME 640 case REALM: 641 setup_realm_context(ctx, ep); 642 break; 643 #endif 644 case NON_SECURE: 645 setup_ns_context(ctx, ep); 646 break; 647 default: 648 ERROR("Invalid security state\n"); 649 panic(); 650 break; 651 } 652 } 653 654 /******************************************************************************* 655 * Enable architecture extensions for EL3 execution. This function only updates 656 * registers in-place which are expected to either never change or be 657 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 658 ******************************************************************************/ 659 #if IMAGE_BL31 660 void cm_manage_extensions_el3(unsigned int my_idx) 661 { 662 if (is_feat_sve_supported()) { 663 sve_init_el3(); 664 } 665 666 if (is_feat_amu_supported()) { 667 amu_init_el3(my_idx); 668 } 669 670 if (is_feat_sme_supported()) { 671 sme_init_el3(); 672 } 673 674 if (is_feat_fgwte3_supported()) { 675 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 676 } 677 pmuv3_init_el3(); 678 } 679 680 /****************************************************************************** 681 * Function to initialise the registers with the RESET values in the context 682 * memory, which are maintained per world. 683 ******************************************************************************/ 684 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 685 { 686 /* 687 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 688 * 689 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 690 * by Advanced SIMD, floating-point or SVE instructions (if 691 * implemented) do not trap to EL3. 692 * 693 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 694 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 695 */ 696 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 697 698 per_world_ctx->ctx_cptr_el3 = cptr_el3; 699 700 /* 701 * Initialize MPAM3_EL3 to its default reset value 702 * 703 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 704 * all lower ELn MPAM3_EL3 register access to, trap to EL3 705 */ 706 707 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 708 } 709 710 /******************************************************************************* 711 * Initialise per_world_context for Non-Secure world. 712 * This function enables the architecture extensions, which have same value 713 * across the cores for the non-secure world. 714 ******************************************************************************/ 715 static void manage_extensions_nonsecure_per_world(void) 716 { 717 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 718 719 if (is_feat_sme_supported()) { 720 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 721 } 722 723 if (is_feat_sve_supported()) { 724 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 725 } 726 727 if (is_feat_amu_supported()) { 728 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 729 } 730 731 if (is_feat_sys_reg_trace_supported()) { 732 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 733 } 734 735 if (is_feat_mpam_supported()) { 736 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 737 } 738 739 if (is_feat_fpmr_supported()) { 740 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 741 } 742 } 743 744 /******************************************************************************* 745 * Initialise per_world_context for Secure world. 746 * This function enables the architecture extensions, which have same value 747 * across the cores for the secure world. 748 ******************************************************************************/ 749 static void manage_extensions_secure_per_world(void) 750 { 751 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 752 753 if (is_feat_sme_supported()) { 754 755 if (ENABLE_SME_FOR_SWD) { 756 /* 757 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 758 * SME, SVE, and FPU/SIMD context properly managed. 759 */ 760 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 761 } else { 762 /* 763 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 764 * world can safely use the associated registers. 765 */ 766 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 767 } 768 } 769 if (is_feat_sve_supported()) { 770 if (ENABLE_SVE_FOR_SWD) { 771 /* 772 * Enable SVE and FPU in secure context, SPM must ensure 773 * that the SVE and FPU register contexts are properly managed. 774 */ 775 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 776 } else { 777 /* 778 * Disable SVE and FPU in secure context so non-secure world 779 * can safely use them. 780 */ 781 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 782 } 783 } 784 785 /* NS can access this but Secure shouldn't */ 786 if (is_feat_sys_reg_trace_supported()) { 787 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 788 } 789 } 790 791 static void manage_extensions_realm_per_world(void) 792 { 793 #if ENABLE_RME 794 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 795 796 if (is_feat_sve_supported()) { 797 /* 798 * Enable SVE and FPU in realm context when it is enabled for NS. 799 * Realm manager must ensure that the SVE and FPU register 800 * contexts are properly managed. 801 */ 802 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 803 } 804 805 /* NS can access this but Realm shouldn't */ 806 if (is_feat_sys_reg_trace_supported()) { 807 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 808 } 809 810 /* 811 * If SME/SME2 is supported and enabled for NS world, then disable trapping 812 * of SME instructions for Realm world. RMM will save/restore required 813 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 814 */ 815 if (is_feat_sme_supported()) { 816 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 817 } 818 819 /* 820 * If FEAT_MPAM is supported and enabled, then disable trapping access 821 * to the MPAM registers for Realm world. Instead, RMM will configure 822 * the access to be trapped by itself so it can inject undefined aborts 823 * back to the Realm. 824 */ 825 if (is_feat_mpam_supported()) { 826 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 827 } 828 #endif /* ENABLE_RME */ 829 } 830 831 void cm_manage_extensions_per_world(void) 832 { 833 manage_extensions_nonsecure_per_world(); 834 manage_extensions_secure_per_world(); 835 manage_extensions_realm_per_world(); 836 } 837 #endif /* IMAGE_BL31 */ 838 839 /******************************************************************************* 840 * Enable architecture extensions on first entry to Non-secure world. 841 ******************************************************************************/ 842 static void manage_extensions_nonsecure(cpu_context_t *ctx) 843 { 844 #if IMAGE_BL31 845 /* NOTE: registers are not context switched */ 846 if (is_feat_amu_supported()) { 847 amu_enable(ctx); 848 } 849 850 if (is_feat_sme_supported()) { 851 sme_enable(ctx); 852 } 853 854 if (is_feat_fgt2_supported()) { 855 fgt2_enable(ctx); 856 } 857 858 if (is_feat_debugv8p9_supported()) { 859 debugv8p9_extended_bp_wp_enable(ctx); 860 } 861 862 /* 863 * SPE, TRBE, and BRBE have multi-field enables that affect which world 864 * they apply to. Despite this, it is useful to ignore these for 865 * simplicity in determining the feature's per world enablement status. 866 * This is only possible when context is written per-world. Relied on 867 * by SMCCC_ARCH_FEATURE_AVAILABILITY 868 */ 869 if (is_feat_spe_supported()) { 870 spe_enable(ctx); 871 } 872 873 if (!check_if_trbe_disable_affected_core()) { 874 if (is_feat_trbe_supported()) { 875 trbe_enable(ctx); 876 } 877 } 878 879 if (is_feat_brbe_supported()) { 880 brbe_enable(ctx); 881 } 882 #endif /* IMAGE_BL31 */ 883 } 884 885 #if INIT_UNUSED_NS_EL2 886 /******************************************************************************* 887 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 888 * world when EL2 is empty and unused. 889 ******************************************************************************/ 890 static void manage_extensions_nonsecure_el2_unused(void) 891 { 892 #if IMAGE_BL31 893 if (is_feat_spe_supported()) { 894 spe_init_el2_unused(); 895 } 896 897 if (is_feat_amu_supported()) { 898 amu_init_el2_unused(); 899 } 900 901 if (is_feat_mpam_supported()) { 902 mpam_init_el2_unused(); 903 } 904 905 if (is_feat_trbe_supported()) { 906 trbe_init_el2_unused(); 907 } 908 909 if (is_feat_sys_reg_trace_supported()) { 910 sys_reg_trace_init_el2_unused(); 911 } 912 913 if (is_feat_trf_supported()) { 914 trf_init_el2_unused(); 915 } 916 917 pmuv3_init_el2_unused(); 918 919 if (is_feat_sve_supported()) { 920 sve_init_el2_unused(); 921 } 922 923 if (is_feat_sme_supported()) { 924 sme_init_el2_unused(); 925 } 926 927 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 928 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 929 } 930 931 if (is_feat_pauth_supported()) { 932 pauth_enable_el2(); 933 } 934 #endif /* IMAGE_BL31 */ 935 } 936 #endif /* INIT_UNUSED_NS_EL2 */ 937 938 /******************************************************************************* 939 * Enable architecture extensions on first entry to Secure world. 940 ******************************************************************************/ 941 static void manage_extensions_secure(cpu_context_t *ctx) 942 { 943 #if IMAGE_BL31 944 if (is_feat_sme_supported()) { 945 if (ENABLE_SME_FOR_SWD) { 946 /* 947 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 948 * must ensure SME, SVE, and FPU/SIMD context properly managed. 949 */ 950 sme_init_el3(); 951 sme_enable(ctx); 952 } else { 953 /* 954 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 955 * world can safely use the associated registers. 956 */ 957 sme_disable(ctx); 958 } 959 } 960 961 /* 962 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 963 * sysreg access can. In case the EL1 controls leave them active on 964 * context switch, we want the owning security state to be NS so Secure 965 * can't be DOSed. 966 */ 967 if (is_feat_spe_supported()) { 968 spe_disable(ctx); 969 } 970 971 if (is_feat_trbe_supported()) { 972 trbe_disable(ctx); 973 } 974 #endif /* IMAGE_BL31 */ 975 } 976 977 /******************************************************************************* 978 * The following function initializes the cpu_context for the current CPU 979 * for first use, and sets the initial entrypoint state as specified by the 980 * entry_point_info structure. 981 ******************************************************************************/ 982 void cm_init_my_context(const entry_point_info_t *ep) 983 { 984 cpu_context_t *ctx; 985 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 986 cm_setup_context(ctx, ep); 987 } 988 989 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 990 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 991 { 992 #if INIT_UNUSED_NS_EL2 993 u_register_t hcr_el2 = HCR_RESET_VAL; 994 u_register_t mdcr_el2; 995 u_register_t scr_el3; 996 997 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 998 999 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1000 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1001 hcr_el2 |= HCR_RW_BIT; 1002 } 1003 1004 write_hcr_el2(hcr_el2); 1005 1006 /* 1007 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1008 * All fields have architecturally UNKNOWN reset values. 1009 */ 1010 write_cptr_el2(CPTR_EL2_RESET_VAL); 1011 1012 /* 1013 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1014 * reset and are set to zero except for field(s) listed below. 1015 * 1016 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1017 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1018 * 1019 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1020 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1021 */ 1022 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1023 1024 /* 1025 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1026 * UNKNOWN value. 1027 */ 1028 write_cntvoff_el2(0); 1029 1030 /* 1031 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1032 * respectively. 1033 */ 1034 write_vpidr_el2(read_midr_el1()); 1035 write_vmpidr_el2(read_mpidr_el1()); 1036 1037 /* 1038 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1039 * 1040 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1041 * translation is disabled, cache maintenance operations depend on the 1042 * VMID. 1043 * 1044 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1045 * disabled. 1046 */ 1047 write_vttbr_el2(VTTBR_RESET_VAL & 1048 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1049 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1050 1051 /* 1052 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1053 * Some fields are architecturally UNKNOWN on reset. 1054 * 1055 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1056 * register accesses to the Debug ROM registers are not trapped to EL2. 1057 * 1058 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1059 * accesses to the powerdown debug registers are not trapped to EL2. 1060 * 1061 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1062 * debug registers do not trap to EL2. 1063 * 1064 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1065 * EL2. 1066 */ 1067 mdcr_el2 = MDCR_EL2_RESET_VAL & 1068 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1069 MDCR_EL2_TDE_BIT); 1070 1071 write_mdcr_el2(mdcr_el2); 1072 1073 /* 1074 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1075 * 1076 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1077 * EL1 accesses to System registers do not trap to EL2. 1078 */ 1079 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1080 1081 /* 1082 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1083 * reset. 1084 * 1085 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1086 * and prevent timer interrupts. 1087 */ 1088 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1089 1090 manage_extensions_nonsecure_el2_unused(); 1091 #endif /* INIT_UNUSED_NS_EL2 */ 1092 } 1093 1094 /******************************************************************************* 1095 * Prepare the CPU system registers for first entry into realm, secure, or 1096 * normal world. 1097 * 1098 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1099 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1100 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1101 * For all entries, the EL1 registers are initialized from the cpu_context 1102 ******************************************************************************/ 1103 void cm_prepare_el3_exit(size_t security_state) 1104 { 1105 u_register_t sctlr_el2, scr_el3; 1106 cpu_context_t *ctx = cm_get_context(security_state); 1107 1108 assert(ctx != NULL); 1109 1110 if (security_state == NON_SECURE) { 1111 uint64_t el2_implemented = el_implemented(2); 1112 1113 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1114 CTX_SCR_EL3); 1115 1116 if (el2_implemented != EL_IMPL_NONE) { 1117 1118 /* 1119 * If context is not being used for EL2, initialize 1120 * HCRX_EL2 with its init value here. 1121 */ 1122 if (is_feat_hcx_supported()) { 1123 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1124 } 1125 1126 /* 1127 * Initialize Fine-grained trap registers introduced 1128 * by FEAT_FGT so all traps are initially disabled when 1129 * switching to EL2 or a lower EL, preventing undesired 1130 * behavior. 1131 */ 1132 if (is_feat_fgt_supported()) { 1133 /* 1134 * Initialize HFG*_EL2 registers with a default 1135 * value so legacy systems unaware of FEAT_FGT 1136 * do not get trapped due to their lack of 1137 * initialization for this feature. 1138 */ 1139 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1140 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1141 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1142 } 1143 1144 /* Condition to ensure EL2 is being used. */ 1145 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1146 /* Initialize SCTLR_EL2 register with reset value. */ 1147 sctlr_el2 = SCTLR_EL2_RES1; 1148 1149 /* 1150 * If workaround of errata 764081 for Cortex-A75 1151 * is used then set SCTLR_EL2.IESB to enable 1152 * Implicit Error Synchronization Barrier. 1153 */ 1154 if (errata_a75_764081_applies()) { 1155 sctlr_el2 |= SCTLR_IESB_BIT; 1156 } 1157 1158 write_sctlr_el2(sctlr_el2); 1159 } else { 1160 /* 1161 * (scr_el3 & SCR_HCE_BIT==0) 1162 * EL2 implemented but unused. 1163 */ 1164 init_nonsecure_el2_unused(ctx); 1165 } 1166 } 1167 1168 if (is_feat_fgwte3_supported()) { 1169 /* 1170 * TCR_EL3 and ACTLR_EL3 could be overwritten 1171 * by platforms and hence is locked a bit late. 1172 */ 1173 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1174 } 1175 } 1176 #if (!CTX_INCLUDE_EL2_REGS) 1177 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1178 cm_el1_sysregs_context_restore(security_state); 1179 #endif 1180 cm_set_next_eret_context(security_state); 1181 } 1182 1183 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1184 1185 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1186 { 1187 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1188 if (is_feat_amu_supported()) { 1189 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1190 } 1191 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1192 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1193 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1194 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1195 } 1196 1197 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1198 { 1199 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1200 if (is_feat_amu_supported()) { 1201 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1202 } 1203 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1204 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1205 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1206 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1207 } 1208 1209 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1210 { 1211 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1212 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1213 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1214 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1215 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1216 } 1217 1218 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1219 { 1220 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1221 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1222 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1223 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1224 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1225 } 1226 1227 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1228 { 1229 u_register_t mpam_idr = read_mpamidr_el1(); 1230 1231 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1232 1233 /* 1234 * The context registers that we intend to save would be part of the 1235 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1236 */ 1237 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1238 return; 1239 } 1240 1241 /* 1242 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1243 * MPAMIDR_HAS_HCR_BIT == 1. 1244 */ 1245 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1246 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1247 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1248 1249 /* 1250 * The number of MPAMVPM registers is implementation defined, their 1251 * number is stored in the MPAMIDR_EL1 register. 1252 */ 1253 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1254 case 7: 1255 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1256 __fallthrough; 1257 case 6: 1258 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1259 __fallthrough; 1260 case 5: 1261 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1262 __fallthrough; 1263 case 4: 1264 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1265 __fallthrough; 1266 case 3: 1267 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1268 __fallthrough; 1269 case 2: 1270 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1271 __fallthrough; 1272 case 1: 1273 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1274 break; 1275 } 1276 } 1277 1278 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1279 { 1280 u_register_t mpam_idr = read_mpamidr_el1(); 1281 1282 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1283 1284 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1285 return; 1286 } 1287 1288 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1289 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1290 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1291 1292 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1293 case 7: 1294 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1295 __fallthrough; 1296 case 6: 1297 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1298 __fallthrough; 1299 case 5: 1300 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1301 __fallthrough; 1302 case 4: 1303 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1304 __fallthrough; 1305 case 3: 1306 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1307 __fallthrough; 1308 case 2: 1309 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1310 __fallthrough; 1311 case 1: 1312 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1313 break; 1314 } 1315 } 1316 1317 /* --------------------------------------------------------------------------- 1318 * The following registers are not added: 1319 * ICH_AP0R<n>_EL2 1320 * ICH_AP1R<n>_EL2 1321 * ICH_LR<n>_EL2 1322 * 1323 * NOTE: For a system with S-EL2 present but not enabled, accessing 1324 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1325 * SCR_EL3.NS = 1 before accessing this register. 1326 * --------------------------------------------------------------------------- 1327 */ 1328 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1329 { 1330 u_register_t scr_el3 = read_scr_el3(); 1331 1332 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1333 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1334 #else 1335 write_scr_el3(scr_el3 | SCR_NS_BIT); 1336 isb(); 1337 1338 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1339 1340 write_scr_el3(scr_el3); 1341 isb(); 1342 #endif 1343 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1344 1345 if (errata_ich_vmcr_el2_applies()) { 1346 if (security_state == SECURE) { 1347 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1348 } else { 1349 write_scr_el3(scr_el3 | SCR_NS_BIT); 1350 } 1351 isb(); 1352 } 1353 1354 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1355 1356 if (errata_ich_vmcr_el2_applies()) { 1357 write_scr_el3(scr_el3); 1358 isb(); 1359 } 1360 } 1361 1362 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1363 { 1364 u_register_t scr_el3 = read_scr_el3(); 1365 1366 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1367 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1368 #else 1369 write_scr_el3(scr_el3 | SCR_NS_BIT); 1370 isb(); 1371 1372 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1373 1374 write_scr_el3(scr_el3); 1375 isb(); 1376 #endif 1377 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1378 1379 if (errata_ich_vmcr_el2_applies()) { 1380 if (security_state == SECURE) { 1381 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1382 } else { 1383 write_scr_el3(scr_el3 | SCR_NS_BIT); 1384 } 1385 isb(); 1386 } 1387 1388 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1389 1390 if (errata_ich_vmcr_el2_applies()) { 1391 write_scr_el3(scr_el3); 1392 isb(); 1393 } 1394 } 1395 1396 /* ----------------------------------------------------- 1397 * The following registers are not added: 1398 * AMEVCNTVOFF0<n>_EL2 1399 * AMEVCNTVOFF1<n>_EL2 1400 * ----------------------------------------------------- 1401 */ 1402 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1403 { 1404 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1405 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1406 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1407 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1408 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1409 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1410 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1411 if (CTX_INCLUDE_AARCH32_REGS) { 1412 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1413 } 1414 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1415 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1416 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1417 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1418 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1419 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1420 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1421 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1422 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1423 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1424 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1425 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1426 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1427 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1428 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1429 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1430 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1431 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1432 1433 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1434 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1435 } 1436 1437 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1438 { 1439 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1440 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1441 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1442 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1443 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1444 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1445 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1446 if (CTX_INCLUDE_AARCH32_REGS) { 1447 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1448 } 1449 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1450 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1451 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1452 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1453 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1454 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1455 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1456 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1457 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1458 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1459 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1460 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1461 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1462 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1463 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1464 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1465 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1466 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1467 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1468 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1469 } 1470 1471 /******************************************************************************* 1472 * Save EL2 sysreg context 1473 ******************************************************************************/ 1474 void cm_el2_sysregs_context_save(uint32_t security_state) 1475 { 1476 cpu_context_t *ctx; 1477 el2_sysregs_t *el2_sysregs_ctx; 1478 1479 ctx = cm_get_context(security_state); 1480 assert(ctx != NULL); 1481 1482 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1483 1484 el2_sysregs_context_save_common(el2_sysregs_ctx); 1485 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1486 1487 if (is_feat_mte2_supported()) { 1488 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1489 } 1490 1491 if (is_feat_mpam_supported()) { 1492 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1493 } 1494 1495 if (is_feat_fgt_supported()) { 1496 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1497 } 1498 1499 if (is_feat_fgt2_supported()) { 1500 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1501 } 1502 1503 if (is_feat_ecv_v2_supported()) { 1504 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1505 } 1506 1507 if (is_feat_vhe_supported()) { 1508 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1509 read_contextidr_el2()); 1510 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1511 } 1512 1513 if (is_feat_ras_supported()) { 1514 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1515 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1516 } 1517 1518 if (is_feat_nv2_supported()) { 1519 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1520 } 1521 1522 if (is_feat_trf_supported()) { 1523 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1524 } 1525 1526 if (is_feat_csv2_2_supported()) { 1527 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1528 read_scxtnum_el2()); 1529 } 1530 1531 if (is_feat_hcx_supported()) { 1532 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1533 } 1534 1535 if (is_feat_tcr2_supported()) { 1536 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1537 } 1538 1539 if (is_feat_sxpie_supported()) { 1540 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1541 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1542 } 1543 1544 if (is_feat_sxpoe_supported()) { 1545 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1546 } 1547 1548 if (is_feat_brbe_supported()) { 1549 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1550 } 1551 1552 if (is_feat_s2pie_supported()) { 1553 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1554 } 1555 1556 if (is_feat_gcs_supported()) { 1557 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1558 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1559 } 1560 1561 if (is_feat_sctlr2_supported()) { 1562 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1563 } 1564 } 1565 1566 /******************************************************************************* 1567 * Restore EL2 sysreg context 1568 ******************************************************************************/ 1569 void cm_el2_sysregs_context_restore(uint32_t security_state) 1570 { 1571 cpu_context_t *ctx; 1572 el2_sysregs_t *el2_sysregs_ctx; 1573 1574 ctx = cm_get_context(security_state); 1575 assert(ctx != NULL); 1576 1577 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1578 1579 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1580 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1581 1582 if (is_feat_mte2_supported()) { 1583 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1584 } 1585 1586 if (is_feat_mpam_supported()) { 1587 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1588 } 1589 1590 if (is_feat_fgt_supported()) { 1591 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1592 } 1593 1594 if (is_feat_fgt2_supported()) { 1595 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1596 } 1597 1598 if (is_feat_ecv_v2_supported()) { 1599 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1600 } 1601 1602 if (is_feat_vhe_supported()) { 1603 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1604 contextidr_el2)); 1605 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1606 } 1607 1608 if (is_feat_ras_supported()) { 1609 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1610 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1611 } 1612 1613 if (is_feat_nv2_supported()) { 1614 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1615 } 1616 1617 if (is_feat_trf_supported()) { 1618 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1619 } 1620 1621 if (is_feat_csv2_2_supported()) { 1622 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1623 scxtnum_el2)); 1624 } 1625 1626 if (is_feat_hcx_supported()) { 1627 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1628 } 1629 1630 if (is_feat_tcr2_supported()) { 1631 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1632 } 1633 1634 if (is_feat_sxpie_supported()) { 1635 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1636 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1637 } 1638 1639 if (is_feat_sxpoe_supported()) { 1640 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1641 } 1642 1643 if (is_feat_s2pie_supported()) { 1644 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1645 } 1646 1647 if (is_feat_gcs_supported()) { 1648 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1649 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1650 } 1651 1652 if (is_feat_sctlr2_supported()) { 1653 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1654 } 1655 1656 if (is_feat_brbe_supported()) { 1657 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1658 } 1659 } 1660 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1661 1662 /******************************************************************************* 1663 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1664 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1665 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1666 * cm_prepare_el3_exit function. 1667 ******************************************************************************/ 1668 void cm_prepare_el3_exit_ns(void) 1669 { 1670 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1671 #if ENABLE_ASSERTIONS 1672 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1673 assert(ctx != NULL); 1674 1675 /* Assert that EL2 is used. */ 1676 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1677 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1678 (el_implemented(2U) != EL_IMPL_NONE)); 1679 #endif /* ENABLE_ASSERTIONS */ 1680 1681 /* Restore EL2 sysreg contexts */ 1682 cm_el2_sysregs_context_restore(NON_SECURE); 1683 cm_set_next_eret_context(NON_SECURE); 1684 #else 1685 cm_prepare_el3_exit(NON_SECURE); 1686 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1687 } 1688 1689 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1690 /******************************************************************************* 1691 * The next set of six functions are used by runtime services to save and restore 1692 * EL1 context on the 'cpu_context' structure for the specified security state. 1693 ******************************************************************************/ 1694 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1695 { 1696 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1697 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1698 1699 #if (!ERRATA_SPECULATIVE_AT) 1700 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1701 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1702 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1703 1704 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1705 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1706 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1707 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1708 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1709 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1710 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1711 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1712 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1713 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1714 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1715 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1716 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1717 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1718 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1719 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1720 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1721 1722 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1723 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1724 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1725 1726 if (CTX_INCLUDE_AARCH32_REGS) { 1727 /* Save Aarch32 registers */ 1728 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1729 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1730 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1731 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1732 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1733 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1734 } 1735 1736 if (NS_TIMER_SWITCH) { 1737 /* Save NS Timer registers */ 1738 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1739 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1740 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1741 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1742 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1743 } 1744 1745 if (is_feat_mte2_supported()) { 1746 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1747 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1748 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1749 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1750 } 1751 1752 if (is_feat_ras_supported()) { 1753 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1754 } 1755 1756 if (is_feat_s1pie_supported()) { 1757 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1758 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1759 } 1760 1761 if (is_feat_s1poe_supported()) { 1762 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1763 } 1764 1765 if (is_feat_s2poe_supported()) { 1766 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1767 } 1768 1769 if (is_feat_tcr2_supported()) { 1770 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1771 } 1772 1773 if (is_feat_trf_supported()) { 1774 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1775 } 1776 1777 if (is_feat_csv2_2_supported()) { 1778 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1779 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1780 } 1781 1782 if (is_feat_gcs_supported()) { 1783 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1784 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1785 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1786 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1787 } 1788 1789 if (is_feat_the_supported()) { 1790 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1791 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1792 } 1793 1794 if (is_feat_sctlr2_supported()) { 1795 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1796 } 1797 1798 if (is_feat_ls64_accdata_supported()) { 1799 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1800 } 1801 } 1802 1803 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1804 { 1805 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1806 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1807 1808 #if (!ERRATA_SPECULATIVE_AT) 1809 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1810 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1811 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1812 1813 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1814 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1815 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1816 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1817 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1818 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1819 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1820 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1821 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1822 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1823 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1824 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1825 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1826 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1827 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1828 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1829 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1830 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1831 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1832 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1833 1834 if (CTX_INCLUDE_AARCH32_REGS) { 1835 /* Restore Aarch32 registers */ 1836 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1837 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1838 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1839 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1840 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1841 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1842 } 1843 1844 if (NS_TIMER_SWITCH) { 1845 /* Restore NS Timer registers */ 1846 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1847 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1848 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1849 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1850 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1851 } 1852 1853 if (is_feat_mte2_supported()) { 1854 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1855 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1856 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1857 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1858 } 1859 1860 if (is_feat_ras_supported()) { 1861 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1862 } 1863 1864 if (is_feat_s1pie_supported()) { 1865 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1866 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1867 } 1868 1869 if (is_feat_s1poe_supported()) { 1870 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1871 } 1872 1873 if (is_feat_s2poe_supported()) { 1874 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1875 } 1876 1877 if (is_feat_tcr2_supported()) { 1878 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1879 } 1880 1881 if (is_feat_trf_supported()) { 1882 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1883 } 1884 1885 if (is_feat_csv2_2_supported()) { 1886 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1887 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1888 } 1889 1890 if (is_feat_gcs_supported()) { 1891 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1892 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1893 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1894 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1895 } 1896 1897 if (is_feat_the_supported()) { 1898 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1899 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1900 } 1901 1902 if (is_feat_sctlr2_supported()) { 1903 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1904 } 1905 1906 if (is_feat_ls64_accdata_supported()) { 1907 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1908 } 1909 } 1910 1911 /******************************************************************************* 1912 * The next couple of functions are used by runtime services to save and restore 1913 * EL1 context on the 'cpu_context' structure for the specified security state. 1914 ******************************************************************************/ 1915 void cm_el1_sysregs_context_save(uint32_t security_state) 1916 { 1917 cpu_context_t *ctx; 1918 1919 ctx = cm_get_context(security_state); 1920 assert(ctx != NULL); 1921 1922 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1923 1924 #if IMAGE_BL31 1925 if (security_state == SECURE) { 1926 PUBLISH_EVENT(cm_exited_secure_world); 1927 } else { 1928 PUBLISH_EVENT(cm_exited_normal_world); 1929 } 1930 #endif 1931 } 1932 1933 void cm_el1_sysregs_context_restore(uint32_t security_state) 1934 { 1935 cpu_context_t *ctx; 1936 1937 ctx = cm_get_context(security_state); 1938 assert(ctx != NULL); 1939 1940 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1941 1942 #if IMAGE_BL31 1943 if (security_state == SECURE) { 1944 PUBLISH_EVENT(cm_entering_secure_world); 1945 } else { 1946 PUBLISH_EVENT(cm_entering_normal_world); 1947 } 1948 #endif 1949 } 1950 1951 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1952 1953 /******************************************************************************* 1954 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1955 * given security state with the given entrypoint 1956 ******************************************************************************/ 1957 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1958 { 1959 cpu_context_t *ctx; 1960 el3_state_t *state; 1961 1962 ctx = cm_get_context(security_state); 1963 assert(ctx != NULL); 1964 1965 /* Populate EL3 state so that ERET jumps to the correct entry */ 1966 state = get_el3state_ctx(ctx); 1967 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1968 } 1969 1970 /******************************************************************************* 1971 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1972 * pertaining to the given security state 1973 ******************************************************************************/ 1974 void cm_set_elr_spsr_el3(uint32_t security_state, 1975 uintptr_t entrypoint, uint32_t spsr) 1976 { 1977 cpu_context_t *ctx; 1978 el3_state_t *state; 1979 1980 ctx = cm_get_context(security_state); 1981 assert(ctx != NULL); 1982 1983 /* Populate EL3 state so that ERET jumps to the correct entry */ 1984 state = get_el3state_ctx(ctx); 1985 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1986 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1987 } 1988 1989 /******************************************************************************* 1990 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1991 * pertaining to the given security state using the value and bit position 1992 * specified in the parameters. It preserves all other bits. 1993 ******************************************************************************/ 1994 void cm_write_scr_el3_bit(uint32_t security_state, 1995 uint32_t bit_pos, 1996 uint32_t value) 1997 { 1998 cpu_context_t *ctx; 1999 el3_state_t *state; 2000 u_register_t scr_el3; 2001 2002 ctx = cm_get_context(security_state); 2003 assert(ctx != NULL); 2004 2005 /* Ensure that the bit position is a valid one */ 2006 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2007 2008 /* Ensure that the 'value' is only a bit wide */ 2009 assert(value <= 1U); 2010 2011 /* 2012 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2013 * and set it to its new value. 2014 */ 2015 state = get_el3state_ctx(ctx); 2016 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2017 scr_el3 &= ~(1UL << bit_pos); 2018 scr_el3 |= (u_register_t)value << bit_pos; 2019 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2020 } 2021 2022 /******************************************************************************* 2023 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2024 * given security state. 2025 ******************************************************************************/ 2026 u_register_t cm_get_scr_el3(uint32_t security_state) 2027 { 2028 const cpu_context_t *ctx; 2029 const el3_state_t *state; 2030 2031 ctx = cm_get_context(security_state); 2032 assert(ctx != NULL); 2033 2034 /* Populate EL3 state so that ERET jumps to the correct entry */ 2035 state = get_el3state_ctx(ctx); 2036 return read_ctx_reg(state, CTX_SCR_EL3); 2037 } 2038 2039 /******************************************************************************* 2040 * This function is used to program the context that's used for exception 2041 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2042 * the required security state 2043 ******************************************************************************/ 2044 void cm_set_next_eret_context(uint32_t security_state) 2045 { 2046 cpu_context_t *ctx; 2047 2048 ctx = cm_get_context(security_state); 2049 assert(ctx != NULL); 2050 2051 cm_set_next_context(ctx); 2052 } 2053