1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <assert.h> 12 #include <common/bl_common.h> 13 #include <drivers/arm/gicv2.h> 14 #include <drivers/ti/uart/uart_16550.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 #include <plat/common/platform.h> 18 19 #include "ccu/ncore_ccu.h" 20 #include "socfpga_mailbox.h" 21 #include "socfpga_private.h" 22 #include "socfpga_sip_svc.h" 23 24 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 25 uint32_t arm_get_spsr_for_bl33_entry(void); 26 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 30 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 31 { 32 entry_point_info_t *next_image_info; 33 34 next_image_info = (type == NON_SECURE) ? 35 &bl33_image_ep_info : &bl32_image_ep_info; 36 37 /* None of the images on this platform can have 0x0 as the entrypoint */ 38 if (next_image_info->pc) 39 return next_image_info; 40 else 41 return NULL; 42 } 43 44 void setup_smmu_secure_context(void) 45 { 46 /* 47 * Program SCR0 register (0xFA000000) 48 * to set SMCFCFG bit[21] to 0x1 which raise stream match conflict fault 49 * to set CLIENTPD bit[0] to 0x0 which enables SMMU for secure context 50 */ 51 mmio_write_32(0xFA000000, 0x00200000); 52 53 /* 54 * Program SCR1 register (0xFA000004) 55 * to set NSNUMSMRGO bit[14:8] to 0x4 which stream mapping register 56 * for non-secure context and the rest will be secure context 57 * to set NSNUMCBO bit[5:0] to 0x4 which allocate context bank 58 * for non-secure context and the rest will be secure context 59 */ 60 mmio_write_32(0xFA000004, 0x00000404); 61 } 62 63 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 64 u_register_t arg2, u_register_t arg3) 65 { 66 static console_t console; 67 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 68 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 69 PLAT_BAUDRATE, &console); 70 71 /* Enable TF-A BL31 logs when running from non-secure world also. */ 72 console_set_scope(&console, 73 (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH)); 74 75 /* 76 * Check params passed from BL31 should not be NULL, 77 */ 78 void *from_bl2 = (void *) arg0; 79 80 #if RESET_TO_BL31 81 /* There are no parameters from BL2 if BL31 is a reset vector */ 82 assert(from_bl2 == NULL); 83 void *plat_params_from_bl2 = (void *) arg3; 84 85 assert(plat_params_from_bl2 == NULL); 86 87 /* Populate entry point information for BL33 */ 88 SET_PARAM_HEAD(&bl33_image_ep_info, 89 PARAM_EP, 90 VERSION_1, 91 0); 92 93 # if ARM_LINUX_KERNEL_AS_BL33 94 /* 95 * According to the file ``Documentation/arm64/booting.txt`` of the 96 * Linux kernel tree, Linux expects the physical address of the device 97 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 98 * must be 0. 99 */ 100 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 101 bl33_image_ep_info.args.arg1 = 0U; 102 bl33_image_ep_info.args.arg2 = 0U; 103 bl33_image_ep_info.args.arg3 = 0U; 104 # endif 105 106 #else /* RESET_TO_BL31 */ 107 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 108 assert(params_from_bl2 != NULL); 109 110 /* 111 * Copy BL32 (if populated by BL31) and BL33 entry point information. 112 * They are stored in Secure RAM, in BL31's address space. 113 */ 114 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 115 params_from_bl2->h.version >= VERSION_2) { 116 bl_params_node_t *bl_params = params_from_bl2->head; 117 while (bl_params) { 118 if (bl_params->image_id == BL33_IMAGE_ID) 119 bl33_image_ep_info = *bl_params->ep_info; 120 bl_params = bl_params->next_params_info; 121 } 122 } else { 123 struct socfpga_bl31_params *arg_from_bl2 = 124 (struct socfpga_bl31_params *) from_bl2; 125 assert(arg_from_bl2->h.type == PARAM_BL31); 126 assert(arg_from_bl2->h.version >= VERSION_1); 127 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 128 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 129 } 130 131 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 132 bl33_image_ep_info.args.arg1 = 0U; 133 bl33_image_ep_info.args.arg2 = 0U; 134 bl33_image_ep_info.args.arg3 = 0U; 135 #endif 136 137 /* 138 * Tell BL31 where the non-trusted software image 139 * is located and the entry state information 140 */ 141 # if ARM_LINUX_KERNEL_AS_BL33 142 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 143 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 144 #endif 145 146 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 147 } 148 149 static const interrupt_prop_t s10_interrupt_props[] = { 150 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 151 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 152 }; 153 154 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 155 156 static const gicv2_driver_data_t plat_gicv2_gic_data = { 157 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 158 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 159 .interrupt_props = s10_interrupt_props, 160 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 161 .target_masks = target_mask_array, 162 .target_masks_num = ARRAY_SIZE(target_mask_array), 163 }; 164 165 /******************************************************************************* 166 * Perform any BL3-1 platform setup code 167 ******************************************************************************/ 168 void bl31_platform_setup(void) 169 { 170 socfpga_delay_timer_init(); 171 172 /* Initialize the gic cpu and distributor interfaces */ 173 gicv2_driver_init(&plat_gicv2_gic_data); 174 gicv2_distif_init(); 175 gicv2_pcpu_distif_init(); 176 gicv2_cpuif_enable(); 177 setup_smmu_secure_context(); 178 179 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 180 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 181 (uint64_t)plat_secondary_cpus_bl31_entry); 182 183 #if SIP_SVC_V3 184 /* 185 * Re-initialize the mailbox to include V3 specific routines. 186 * In V3, this re-initialize is required because prior to BL31, U-Boot 187 * SPL has its own mailbox settings and this initialization will 188 * override to those settings as required by the V3 framework. 189 */ 190 mailbox_init(); 191 #endif 192 193 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 194 } 195 196 const mmap_region_t plat_agilex_mmap[] = { 197 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 198 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), 199 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 200 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 201 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 202 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 203 MT_DEVICE | MT_RW | MT_SECURE), 204 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 205 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), 206 {0} 207 }; 208 209 /******************************************************************************* 210 * Perform the very early platform specific architectural setup here. At the 211 * moment this is only initializes the mmu in a quick and dirty way. 212 ******************************************************************************/ 213 void bl31_plat_arch_setup(void) 214 { 215 const mmap_region_t bl_regions[] = { 216 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 217 MT_MEMORY | MT_RW | MT_SECURE), 218 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 219 MT_CODE | MT_SECURE), 220 MAP_REGION_FLAT(BL_RO_DATA_BASE, 221 BL_RO_DATA_END - BL_RO_DATA_BASE, 222 MT_RO_DATA | MT_SECURE), 223 #if USE_COHERENT_MEM 224 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 225 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 226 MT_DEVICE | MT_RW | MT_SECURE), 227 #endif 228 {0} 229 }; 230 setup_page_tables(bl_regions, plat_agilex_mmap); 231 enable_mmu_el3(0); 232 } 233 234 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 235 uintptr_t plat_get_ns_image_entrypoint(void) 236 { 237 #ifdef PRELOADED_BL33_BASE 238 return PRELOADED_BL33_BASE; 239 #else 240 return PLAT_NS_IMAGE_OFFSET; 241 #endif 242 } 243 244 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 245 uint32_t arm_get_spsr_for_bl33_entry(void) 246 { 247 unsigned int mode; 248 uint32_t spsr; 249 250 /* Figure out what mode we enter the non-secure world in */ 251 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 252 253 /* 254 * TODO: Consider the possibility of specifying the SPSR in 255 * the FIP ToC and allowing the platform to have a say as 256 * well. 257 */ 258 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 259 return spsr; 260 } 261