1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 195 if (is_feat_fgt2_supported()) { 196 fgt2_enable(ctx); 197 } 198 199 if (is_feat_debugv8p9_supported()) { 200 debugv8p9_extended_bp_wp_enable(ctx); 201 } 202 203 if (is_feat_brbe_supported()) { 204 brbe_enable(ctx); 205 } 206 207 } 208 #endif /* ENABLE_RME */ 209 210 /****************************************************************************** 211 * This function performs initializations that are specific to NON-SECURE state 212 * and updates the cpu context specified by 'ctx'. 213 *****************************************************************************/ 214 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 215 { 216 u_register_t scr_el3; 217 el3_state_t *state; 218 219 state = get_el3state_ctx(ctx); 220 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 221 222 /* SCR_NS: Set the NS bit */ 223 scr_el3 |= SCR_NS_BIT; 224 225 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 226 if (is_feat_mte2_supported()) { 227 scr_el3 |= SCR_ATA_BIT; 228 } 229 230 #if !CTX_INCLUDE_PAUTH_REGS 231 /* 232 * Pointer Authentication feature, if present, is always enabled by default 233 * for Non secure lower exception levels. We do not have an explicit 234 * flag to set it. 235 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 236 * exception levels of secure and realm worlds. 237 * 238 * To prevent the leakage between the worlds during world switch, 239 * we enable it only for the non-secure world. 240 * 241 * If the Secure/realm world wants to use pointer authentication, 242 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 243 * it will be enabled globally for all the contexts. 244 * 245 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 246 * other than EL3 247 * 248 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 249 * than EL3 250 */ 251 if (is_armv8_3_pauth_present()) { 252 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 253 } 254 #endif /* CTX_INCLUDE_PAUTH_REGS */ 255 256 #if HANDLE_EA_EL3_FIRST_NS 257 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 258 scr_el3 |= SCR_EA_BIT; 259 #endif 260 261 #if RAS_TRAP_NS_ERR_REC_ACCESS 262 /* 263 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 264 * and RAS ERX registers from EL1 and EL2(from any security state) 265 * are trapped to EL3. 266 * Set here to trap only for NS EL1/EL2 267 */ 268 scr_el3 |= SCR_TERR_BIT; 269 #endif 270 271 /* CSV2 version 2 and above */ 272 if (is_feat_csv2_2_supported()) { 273 /* Enable access to the SCXTNUM_ELx registers. */ 274 scr_el3 |= SCR_EnSCXT_BIT; 275 } 276 277 #ifdef IMAGE_BL31 278 /* 279 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 280 * indicated by the interrupt routing model for BL31. 281 */ 282 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 283 #endif 284 285 if (is_feat_the_supported()) { 286 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 287 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 288 */ 289 scr_el3 |= SCR_RCWMASKEn_BIT; 290 } 291 292 if (is_feat_sctlr2_supported()) { 293 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 294 * SCTLR2_ELx registers. 295 */ 296 scr_el3 |= SCR_SCTLR2En_BIT; 297 } 298 299 if (is_feat_d128_supported()) { 300 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 301 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 302 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 303 */ 304 scr_el3 |= SCR_D128En_BIT; 305 } 306 307 if (is_feat_fpmr_supported()) { 308 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 309 * register. 310 */ 311 scr_el3 |= SCR_EnFPM_BIT; 312 } 313 314 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 315 316 /* Initialize EL2 context registers */ 317 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 318 319 /* 320 * Initialize SCTLR_EL2 context register with reset value. 321 */ 322 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 323 324 if (is_feat_hcx_supported()) { 325 /* 326 * Initialize register HCRX_EL2 with its init value. 327 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 328 * chance that this can lead to unexpected behavior in lower 329 * ELs that have not been updated since the introduction of 330 * this feature if not properly initialized, especially when 331 * it comes to those bits that enable/disable traps. 332 */ 333 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 334 HCRX_EL2_INIT_VAL); 335 } 336 337 if (is_feat_fgt_supported()) { 338 /* 339 * Initialize HFG*_EL2 registers with a default value so legacy 340 * systems unaware of FEAT_FGT do not get trapped due to their lack 341 * of initialization for this feature. 342 */ 343 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 344 HFGITR_EL2_INIT_VAL); 345 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 346 HFGRTR_EL2_INIT_VAL); 347 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 348 HFGWTR_EL2_INIT_VAL); 349 } 350 #else 351 /* Initialize EL1 context registers */ 352 setup_el1_context(ctx, ep); 353 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 354 355 manage_extensions_nonsecure(ctx); 356 } 357 358 /******************************************************************************* 359 * The following function performs initialization of the cpu_context 'ctx' 360 * for first use that is common to all security states, and sets the 361 * initial entrypoint state as specified by the entry_point_info structure. 362 * 363 * The EE and ST attributes are used to configure the endianness and secure 364 * timer availability for the new execution context. 365 ******************************************************************************/ 366 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 367 { 368 u_register_t scr_el3; 369 u_register_t mdcr_el3; 370 el3_state_t *state; 371 gp_regs_t *gp_regs; 372 373 state = get_el3state_ctx(ctx); 374 375 /* Clear any residual register values from the context */ 376 zeromem(ctx, sizeof(*ctx)); 377 378 /* 379 * The lower-EL context is zeroed so that no stale values leak to a world. 380 * It is assumed that an all-zero lower-EL context is good enough for it 381 * to boot correctly. However, there are very few registers where this 382 * is not true and some values need to be recreated. 383 */ 384 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 385 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 386 387 /* 388 * These bits are set in the gicv3 driver. Losing them (especially the 389 * SRE bit) is problematic for all worlds. Henceforth recreate them. 390 */ 391 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 392 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 393 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 394 395 /* 396 * The actlr_el2 register can be initialized in platform's reset handler 397 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 398 */ 399 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 400 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 401 402 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 403 scr_el3 = SCR_RESET_VAL; 404 405 /* 406 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 407 * EL2, EL1 and EL0 are not trapped to EL3. 408 * 409 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 410 * EL2, EL1 and EL0 are not trapped to EL3. 411 * 412 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 413 * both Security states and both Execution states. 414 * 415 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 416 * Non-secure memory. 417 */ 418 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 419 420 scr_el3 |= SCR_SIF_BIT; 421 422 /* 423 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 424 * Exception level as specified by SPSR. 425 */ 426 if (GET_RW(ep->spsr) == MODE_RW_64) { 427 scr_el3 |= SCR_RW_BIT; 428 } 429 430 /* 431 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 432 * Secure timer registers to EL3, from AArch64 state only, if specified 433 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 434 * bit always behaves as 1 (i.e. secure physical timer register access 435 * is not trapped) 436 */ 437 if (EP_GET_ST(ep->h.attr) != 0U) { 438 scr_el3 |= SCR_ST_BIT; 439 } 440 441 /* 442 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 443 * SCR_EL3.HXEn. 444 */ 445 if (is_feat_hcx_supported()) { 446 scr_el3 |= SCR_HXEn_BIT; 447 } 448 449 /* 450 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 451 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 452 * SCR_EL3.EnAS0. 453 */ 454 if (is_feat_ls64_accdata_supported()) { 455 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 456 } 457 458 /* 459 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 460 * registers are trapped to EL3. 461 */ 462 if (is_feat_rng_trap_supported()) { 463 scr_el3 |= SCR_TRNDR_BIT; 464 } 465 466 #if FAULT_INJECTION_SUPPORT 467 /* Enable fault injection from lower ELs */ 468 scr_el3 |= SCR_FIEN_BIT; 469 #endif 470 471 #if CTX_INCLUDE_PAUTH_REGS 472 /* 473 * Enable Pointer Authentication globally for all the worlds. 474 * 475 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 476 * other than EL3 477 * 478 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 479 * than EL3 480 */ 481 if (is_armv8_3_pauth_present()) { 482 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 483 } 484 #endif /* CTX_INCLUDE_PAUTH_REGS */ 485 486 /* 487 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 488 */ 489 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 490 scr_el3 |= SCR_TCR2EN_BIT; 491 } 492 493 /* 494 * SCR_EL3.PIEN: Enable permission indirection and overlay 495 * registers for AArch64 if present. 496 */ 497 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 498 scr_el3 |= SCR_PIEN_BIT; 499 } 500 501 /* 502 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 503 */ 504 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 505 scr_el3 |= SCR_GCSEn_BIT; 506 } 507 508 /* 509 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 510 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 511 * next mode is Hyp. 512 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 513 * same conditions as HVC instructions and when the processor supports 514 * ARMv8.6-FGT. 515 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 516 * CNTPOFF_EL2 register under the same conditions as HVC instructions 517 * and when the processor supports ECV. 518 */ 519 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 520 || ((GET_RW(ep->spsr) != MODE_RW_64) 521 && (GET_M32(ep->spsr) == MODE32_hyp))) { 522 scr_el3 |= SCR_HCE_BIT; 523 524 if (is_feat_fgt_supported()) { 525 scr_el3 |= SCR_FGTEN_BIT; 526 } 527 528 if (is_feat_ecv_supported()) { 529 scr_el3 |= SCR_ECVEN_BIT; 530 } 531 } 532 533 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 534 if (is_feat_twed_supported()) { 535 /* Set delay in SCR_EL3 */ 536 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 537 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 538 << SCR_TWEDEL_SHIFT); 539 540 /* Enable WFE delay */ 541 scr_el3 |= SCR_TWEDEn_BIT; 542 } 543 544 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 545 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 546 if (is_feat_sel2_supported()) { 547 scr_el3 |= SCR_EEL2_BIT; 548 } 549 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 550 551 /* 552 * Populate EL3 state so that we've the right context 553 * before doing ERET 554 */ 555 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 556 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 557 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 558 559 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 560 mdcr_el3 = MDCR_EL3_RESET_VAL; 561 562 /* --------------------------------------------------------------------- 563 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 564 * Some fields are architecturally UNKNOWN on reset. 565 * 566 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 567 * Debug exceptions, other than Breakpoint Instruction exceptions, are 568 * disabled from all ELs in Secure state. 569 * 570 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 571 * privileged debug from S-EL1. 572 * 573 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 574 * access to the powerdown debug registers do not trap to EL3. 575 * 576 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 577 * debug registers, other than those registers that are controlled by 578 * MDCR_EL3.TDOSA. 579 */ 580 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 581 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 582 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 583 584 #if IMAGE_BL31 585 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 586 if (is_feat_trf_supported()) { 587 trf_enable(ctx); 588 } 589 590 pmuv3_enable(ctx); 591 #endif /* IMAGE_BL31 */ 592 593 /* 594 * Store the X0-X7 value from the entrypoint into the context 595 * Use memcpy as we are in control of the layout of the structures 596 */ 597 gp_regs = get_gpregs_ctx(ctx); 598 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 599 } 600 601 /******************************************************************************* 602 * Context management library initialization routine. This library is used by 603 * runtime services to share pointers to 'cpu_context' structures for secure 604 * non-secure and realm states. Management of the structures and their associated 605 * memory is not done by the context management library e.g. the PSCI service 606 * manages the cpu context used for entry from and exit to the non-secure state. 607 * The Secure payload dispatcher service manages the context(s) corresponding to 608 * the secure state. It also uses this library to get access to the non-secure 609 * state cpu context pointers. 610 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 611 * which will be used for programming an entry into a lower EL. The same context 612 * will be used to save state upon exception entry from that EL. 613 ******************************************************************************/ 614 void __init cm_init(void) 615 { 616 /* 617 * The context management library has only global data to initialize, but 618 * that will be done when the BSS is zeroed out. 619 */ 620 } 621 622 /******************************************************************************* 623 * This is the high-level function used to initialize the cpu_context 'ctx' for 624 * first use. It performs initializations that are common to all security states 625 * and initializations specific to the security state specified in 'ep' 626 ******************************************************************************/ 627 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 628 { 629 unsigned int security_state; 630 631 assert(ctx != NULL); 632 633 /* 634 * Perform initializations that are common 635 * to all security states 636 */ 637 setup_context_common(ctx, ep); 638 639 security_state = GET_SECURITY_STATE(ep->h.attr); 640 641 /* Perform security state specific initializations */ 642 switch (security_state) { 643 case SECURE: 644 setup_secure_context(ctx, ep); 645 break; 646 #if ENABLE_RME 647 case REALM: 648 setup_realm_context(ctx, ep); 649 break; 650 #endif 651 case NON_SECURE: 652 setup_ns_context(ctx, ep); 653 break; 654 default: 655 ERROR("Invalid security state\n"); 656 panic(); 657 break; 658 } 659 } 660 661 /******************************************************************************* 662 * Enable architecture extensions for EL3 execution. This function only updates 663 * registers in-place which are expected to either never change or be 664 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 665 ******************************************************************************/ 666 #if IMAGE_BL31 667 void cm_manage_extensions_el3(unsigned int my_idx) 668 { 669 if (is_feat_amu_supported()) { 670 amu_init_el3(my_idx); 671 } 672 673 if (is_feat_sme_supported()) { 674 sme_init_el3(); 675 } 676 677 pmuv3_init_el3(); 678 } 679 #endif /* IMAGE_BL31 */ 680 681 /****************************************************************************** 682 * Function to initialise the registers with the RESET values in the context 683 * memory, which are maintained per world. 684 ******************************************************************************/ 685 #if IMAGE_BL31 686 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 687 { 688 /* 689 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 690 * 691 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 692 * by Advanced SIMD, floating-point or SVE instructions (if 693 * implemented) do not trap to EL3. 694 * 695 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 696 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 697 */ 698 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 699 700 per_world_ctx->ctx_cptr_el3 = cptr_el3; 701 702 /* 703 * Initialize MPAM3_EL3 to its default reset value 704 * 705 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 706 * all lower ELn MPAM3_EL3 register access to, trap to EL3 707 */ 708 709 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 710 } 711 #endif /* IMAGE_BL31 */ 712 713 /******************************************************************************* 714 * Initialise per_world_context for Non-Secure world. 715 * This function enables the architecture extensions, which have same value 716 * across the cores for the non-secure world. 717 ******************************************************************************/ 718 #if IMAGE_BL31 719 void manage_extensions_nonsecure_per_world(void) 720 { 721 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 722 723 if (is_feat_sme_supported()) { 724 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 725 } 726 727 if (is_feat_sve_supported()) { 728 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 729 } 730 731 if (is_feat_amu_supported()) { 732 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 733 } 734 735 if (is_feat_sys_reg_trace_supported()) { 736 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 737 } 738 739 if (is_feat_mpam_supported()) { 740 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 741 } 742 743 if (is_feat_fpmr_supported()) { 744 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 745 } 746 } 747 #endif /* IMAGE_BL31 */ 748 749 /******************************************************************************* 750 * Initialise per_world_context for Secure world. 751 * This function enables the architecture extensions, which have same value 752 * across the cores for the secure world. 753 ******************************************************************************/ 754 static void manage_extensions_secure_per_world(void) 755 { 756 #if IMAGE_BL31 757 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 758 759 if (is_feat_sme_supported()) { 760 761 if (ENABLE_SME_FOR_SWD) { 762 /* 763 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 764 * SME, SVE, and FPU/SIMD context properly managed. 765 */ 766 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 767 } else { 768 /* 769 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 770 * world can safely use the associated registers. 771 */ 772 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 773 } 774 } 775 if (is_feat_sve_supported()) { 776 if (ENABLE_SVE_FOR_SWD) { 777 /* 778 * Enable SVE and FPU in secure context, SPM must ensure 779 * that the SVE and FPU register contexts are properly managed. 780 */ 781 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 782 } else { 783 /* 784 * Disable SVE and FPU in secure context so non-secure world 785 * can safely use them. 786 */ 787 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 788 } 789 } 790 791 /* NS can access this but Secure shouldn't */ 792 if (is_feat_sys_reg_trace_supported()) { 793 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 794 } 795 796 has_secure_perworld_init = true; 797 #endif /* IMAGE_BL31 */ 798 } 799 800 /******************************************************************************* 801 * Enable architecture extensions on first entry to Non-secure world. 802 ******************************************************************************/ 803 static void manage_extensions_nonsecure(cpu_context_t *ctx) 804 { 805 #if IMAGE_BL31 806 /* NOTE: registers are not context switched */ 807 if (is_feat_amu_supported()) { 808 amu_enable(ctx); 809 } 810 811 if (is_feat_sme_supported()) { 812 sme_enable(ctx); 813 } 814 815 if (is_feat_fgt2_supported()) { 816 fgt2_enable(ctx); 817 } 818 819 if (is_feat_debugv8p9_supported()) { 820 debugv8p9_extended_bp_wp_enable(ctx); 821 } 822 823 /* 824 * SPE, TRBE, and BRBE have multi-field enables that affect which world 825 * they apply to. Despite this, it is useful to ignore these for 826 * simplicity in determining the feature's per world enablement status. 827 * This is only possible when context is written per-world. Relied on 828 * by SMCCC_ARCH_FEATURE_AVAILABILITY 829 */ 830 if (is_feat_spe_supported()) { 831 spe_enable(ctx); 832 } 833 834 if (is_feat_trbe_supported()) { 835 trbe_enable(ctx); 836 } 837 838 if (is_feat_brbe_supported()) { 839 brbe_enable(ctx); 840 } 841 #endif /* IMAGE_BL31 */ 842 } 843 844 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 845 static __unused void enable_pauth_el2(void) 846 { 847 u_register_t hcr_el2 = read_hcr_el2(); 848 /* 849 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 850 * accessing key registers or using pointer authentication instructions 851 * from lower ELs. 852 */ 853 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 854 855 write_hcr_el2(hcr_el2); 856 } 857 858 #if INIT_UNUSED_NS_EL2 859 /******************************************************************************* 860 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 861 * world when EL2 is empty and unused. 862 ******************************************************************************/ 863 static void manage_extensions_nonsecure_el2_unused(void) 864 { 865 #if IMAGE_BL31 866 if (is_feat_spe_supported()) { 867 spe_init_el2_unused(); 868 } 869 870 if (is_feat_amu_supported()) { 871 amu_init_el2_unused(); 872 } 873 874 if (is_feat_mpam_supported()) { 875 mpam_init_el2_unused(); 876 } 877 878 if (is_feat_trbe_supported()) { 879 trbe_init_el2_unused(); 880 } 881 882 if (is_feat_sys_reg_trace_supported()) { 883 sys_reg_trace_init_el2_unused(); 884 } 885 886 if (is_feat_trf_supported()) { 887 trf_init_el2_unused(); 888 } 889 890 pmuv3_init_el2_unused(); 891 892 if (is_feat_sve_supported()) { 893 sve_init_el2_unused(); 894 } 895 896 if (is_feat_sme_supported()) { 897 sme_init_el2_unused(); 898 } 899 900 if (is_feat_mops_supported()) { 901 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 902 } 903 904 #if ENABLE_PAUTH 905 enable_pauth_el2(); 906 #endif /* ENABLE_PAUTH */ 907 #endif /* IMAGE_BL31 */ 908 } 909 #endif /* INIT_UNUSED_NS_EL2 */ 910 911 /******************************************************************************* 912 * Enable architecture extensions on first entry to Secure world. 913 ******************************************************************************/ 914 static void manage_extensions_secure(cpu_context_t *ctx) 915 { 916 #if IMAGE_BL31 917 if (is_feat_sme_supported()) { 918 if (ENABLE_SME_FOR_SWD) { 919 /* 920 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 921 * must ensure SME, SVE, and FPU/SIMD context properly managed. 922 */ 923 sme_init_el3(); 924 sme_enable(ctx); 925 } else { 926 /* 927 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 928 * world can safely use the associated registers. 929 */ 930 sme_disable(ctx); 931 } 932 } 933 934 /* 935 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 936 * sysreg access can. In case the EL1 controls leave them active on 937 * context switch, we want the owning security state to be NS so Secure 938 * can't be DOSed. 939 */ 940 if (is_feat_spe_supported()) { 941 spe_disable(ctx); 942 } 943 944 if (is_feat_trbe_supported()) { 945 trbe_disable(ctx); 946 } 947 #endif /* IMAGE_BL31 */ 948 } 949 950 #if !IMAGE_BL1 951 /******************************************************************************* 952 * The following function initializes the cpu_context for a CPU specified by 953 * its `cpu_idx` for first use, and sets the initial entrypoint state as 954 * specified by the entry_point_info structure. 955 ******************************************************************************/ 956 void cm_init_context_by_index(unsigned int cpu_idx, 957 const entry_point_info_t *ep) 958 { 959 cpu_context_t *ctx; 960 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 961 cm_setup_context(ctx, ep); 962 } 963 #endif /* !IMAGE_BL1 */ 964 965 /******************************************************************************* 966 * The following function initializes the cpu_context for the current CPU 967 * for first use, and sets the initial entrypoint state as specified by the 968 * entry_point_info structure. 969 ******************************************************************************/ 970 void cm_init_my_context(const entry_point_info_t *ep) 971 { 972 cpu_context_t *ctx; 973 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 974 cm_setup_context(ctx, ep); 975 } 976 977 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 978 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 979 { 980 #if INIT_UNUSED_NS_EL2 981 u_register_t hcr_el2 = HCR_RESET_VAL; 982 u_register_t mdcr_el2; 983 u_register_t scr_el3; 984 985 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 986 987 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 988 if ((scr_el3 & SCR_RW_BIT) != 0U) { 989 hcr_el2 |= HCR_RW_BIT; 990 } 991 992 write_hcr_el2(hcr_el2); 993 994 /* 995 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 996 * All fields have architecturally UNKNOWN reset values. 997 */ 998 write_cptr_el2(CPTR_EL2_RESET_VAL); 999 1000 /* 1001 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1002 * reset and are set to zero except for field(s) listed below. 1003 * 1004 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1005 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1006 * 1007 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1008 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1009 */ 1010 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1011 1012 /* 1013 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1014 * UNKNOWN value. 1015 */ 1016 write_cntvoff_el2(0); 1017 1018 /* 1019 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1020 * respectively. 1021 */ 1022 write_vpidr_el2(read_midr_el1()); 1023 write_vmpidr_el2(read_mpidr_el1()); 1024 1025 /* 1026 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1027 * 1028 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1029 * translation is disabled, cache maintenance operations depend on the 1030 * VMID. 1031 * 1032 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1033 * disabled. 1034 */ 1035 write_vttbr_el2(VTTBR_RESET_VAL & 1036 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1037 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1038 1039 /* 1040 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1041 * Some fields are architecturally UNKNOWN on reset. 1042 * 1043 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1044 * register accesses to the Debug ROM registers are not trapped to EL2. 1045 * 1046 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1047 * accesses to the powerdown debug registers are not trapped to EL2. 1048 * 1049 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1050 * debug registers do not trap to EL2. 1051 * 1052 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1053 * EL2. 1054 */ 1055 mdcr_el2 = MDCR_EL2_RESET_VAL & 1056 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1057 MDCR_EL2_TDE_BIT); 1058 1059 write_mdcr_el2(mdcr_el2); 1060 1061 /* 1062 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1063 * 1064 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1065 * EL1 accesses to System registers do not trap to EL2. 1066 */ 1067 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1068 1069 /* 1070 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1071 * reset. 1072 * 1073 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1074 * and prevent timer interrupts. 1075 */ 1076 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1077 1078 manage_extensions_nonsecure_el2_unused(); 1079 #endif /* INIT_UNUSED_NS_EL2 */ 1080 } 1081 1082 /******************************************************************************* 1083 * Prepare the CPU system registers for first entry into realm, secure, or 1084 * normal world. 1085 * 1086 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1087 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1088 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1089 * For all entries, the EL1 registers are initialized from the cpu_context 1090 ******************************************************************************/ 1091 void cm_prepare_el3_exit(uint32_t security_state) 1092 { 1093 u_register_t sctlr_el2, scr_el3; 1094 cpu_context_t *ctx = cm_get_context(security_state); 1095 1096 assert(ctx != NULL); 1097 1098 if (security_state == NON_SECURE) { 1099 uint64_t el2_implemented = el_implemented(2); 1100 1101 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1102 CTX_SCR_EL3); 1103 1104 if (el2_implemented != EL_IMPL_NONE) { 1105 1106 /* 1107 * If context is not being used for EL2, initialize 1108 * HCRX_EL2 with its init value here. 1109 */ 1110 if (is_feat_hcx_supported()) { 1111 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1112 } 1113 1114 /* 1115 * Initialize Fine-grained trap registers introduced 1116 * by FEAT_FGT so all traps are initially disabled when 1117 * switching to EL2 or a lower EL, preventing undesired 1118 * behavior. 1119 */ 1120 if (is_feat_fgt_supported()) { 1121 /* 1122 * Initialize HFG*_EL2 registers with a default 1123 * value so legacy systems unaware of FEAT_FGT 1124 * do not get trapped due to their lack of 1125 * initialization for this feature. 1126 */ 1127 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1128 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1129 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1130 } 1131 1132 /* Condition to ensure EL2 is being used. */ 1133 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1134 /* Initialize SCTLR_EL2 register with reset value. */ 1135 sctlr_el2 = SCTLR_EL2_RES1; 1136 1137 /* 1138 * If workaround of errata 764081 for Cortex-A75 1139 * is used then set SCTLR_EL2.IESB to enable 1140 * Implicit Error Synchronization Barrier. 1141 */ 1142 if (errata_a75_764081_applies()) { 1143 sctlr_el2 |= SCTLR_IESB_BIT; 1144 } 1145 1146 write_sctlr_el2(sctlr_el2); 1147 } else { 1148 /* 1149 * (scr_el3 & SCR_HCE_BIT==0) 1150 * EL2 implemented but unused. 1151 */ 1152 init_nonsecure_el2_unused(ctx); 1153 } 1154 } 1155 } 1156 #if (!CTX_INCLUDE_EL2_REGS) 1157 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1158 cm_el1_sysregs_context_restore(security_state); 1159 #endif 1160 cm_set_next_eret_context(security_state); 1161 } 1162 1163 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1164 1165 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1166 { 1167 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1168 if (is_feat_amu_supported()) { 1169 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1170 } 1171 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1172 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1173 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1174 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1175 } 1176 1177 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1178 { 1179 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1180 if (is_feat_amu_supported()) { 1181 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1182 } 1183 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1184 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1185 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1186 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1187 } 1188 1189 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1190 { 1191 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1192 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1193 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1194 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1195 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1196 } 1197 1198 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1199 { 1200 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1201 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1202 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1203 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1204 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1205 } 1206 1207 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1208 { 1209 u_register_t mpam_idr = read_mpamidr_el1(); 1210 1211 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1212 1213 /* 1214 * The context registers that we intend to save would be part of the 1215 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1216 */ 1217 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1218 return; 1219 } 1220 1221 /* 1222 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1223 * MPAMIDR_HAS_HCR_BIT == 1. 1224 */ 1225 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1226 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1227 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1228 1229 /* 1230 * The number of MPAMVPM registers is implementation defined, their 1231 * number is stored in the MPAMIDR_EL1 register. 1232 */ 1233 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1234 case 7: 1235 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1236 __fallthrough; 1237 case 6: 1238 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1239 __fallthrough; 1240 case 5: 1241 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1242 __fallthrough; 1243 case 4: 1244 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1245 __fallthrough; 1246 case 3: 1247 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1248 __fallthrough; 1249 case 2: 1250 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1251 __fallthrough; 1252 case 1: 1253 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1254 break; 1255 } 1256 } 1257 1258 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1259 { 1260 u_register_t mpam_idr = read_mpamidr_el1(); 1261 1262 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1263 1264 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1265 return; 1266 } 1267 1268 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1269 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1270 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1271 1272 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1273 case 7: 1274 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1275 __fallthrough; 1276 case 6: 1277 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1278 __fallthrough; 1279 case 5: 1280 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1281 __fallthrough; 1282 case 4: 1283 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1284 __fallthrough; 1285 case 3: 1286 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1287 __fallthrough; 1288 case 2: 1289 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1290 __fallthrough; 1291 case 1: 1292 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1293 break; 1294 } 1295 } 1296 1297 /* --------------------------------------------------------------------------- 1298 * The following registers are not added: 1299 * ICH_AP0R<n>_EL2 1300 * ICH_AP1R<n>_EL2 1301 * ICH_LR<n>_EL2 1302 * 1303 * NOTE: For a system with S-EL2 present but not enabled, accessing 1304 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1305 * SCR_EL3.NS = 1 before accessing this register. 1306 * --------------------------------------------------------------------------- 1307 */ 1308 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1309 { 1310 u_register_t scr_el3 = read_scr_el3(); 1311 1312 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1313 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1314 #else 1315 write_scr_el3(scr_el3 | SCR_NS_BIT); 1316 isb(); 1317 1318 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1319 1320 write_scr_el3(scr_el3); 1321 isb(); 1322 #endif 1323 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1324 1325 if (errata_ich_vmcr_el2_applies()) { 1326 if (security_state == SECURE) { 1327 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1328 } else { 1329 write_scr_el3(scr_el3 | SCR_NS_BIT); 1330 } 1331 isb(); 1332 } 1333 1334 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1335 1336 if (errata_ich_vmcr_el2_applies()) { 1337 write_scr_el3(scr_el3); 1338 isb(); 1339 } 1340 } 1341 1342 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1343 { 1344 u_register_t scr_el3 = read_scr_el3(); 1345 1346 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1347 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1348 #else 1349 write_scr_el3(scr_el3 | SCR_NS_BIT); 1350 isb(); 1351 1352 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1353 1354 write_scr_el3(scr_el3); 1355 isb(); 1356 #endif 1357 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1358 1359 if (errata_ich_vmcr_el2_applies()) { 1360 if (security_state == SECURE) { 1361 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1362 } else { 1363 write_scr_el3(scr_el3 | SCR_NS_BIT); 1364 } 1365 isb(); 1366 } 1367 1368 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1369 1370 if (errata_ich_vmcr_el2_applies()) { 1371 write_scr_el3(scr_el3); 1372 isb(); 1373 } 1374 } 1375 1376 /* ----------------------------------------------------- 1377 * The following registers are not added: 1378 * AMEVCNTVOFF0<n>_EL2 1379 * AMEVCNTVOFF1<n>_EL2 1380 * ----------------------------------------------------- 1381 */ 1382 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1383 { 1384 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1385 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1386 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1387 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1388 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1389 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1390 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1391 if (CTX_INCLUDE_AARCH32_REGS) { 1392 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1393 } 1394 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1395 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1396 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1397 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1398 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1399 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1400 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1401 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1402 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1403 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1404 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1405 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1406 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1407 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1408 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1409 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1410 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1411 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1412 1413 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1414 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1415 } 1416 1417 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1418 { 1419 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1420 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1421 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1422 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1423 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1424 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1425 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1426 if (CTX_INCLUDE_AARCH32_REGS) { 1427 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1428 } 1429 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1430 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1431 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1432 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1433 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1434 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1435 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1436 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1437 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1438 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1439 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1440 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1441 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1442 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1443 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1444 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1445 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1446 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1447 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1448 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1449 } 1450 1451 /******************************************************************************* 1452 * Save EL2 sysreg context 1453 ******************************************************************************/ 1454 void cm_el2_sysregs_context_save(uint32_t security_state) 1455 { 1456 cpu_context_t *ctx; 1457 el2_sysregs_t *el2_sysregs_ctx; 1458 1459 ctx = cm_get_context(security_state); 1460 assert(ctx != NULL); 1461 1462 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1463 1464 el2_sysregs_context_save_common(el2_sysregs_ctx); 1465 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1466 1467 if (is_feat_mte2_supported()) { 1468 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1469 } 1470 1471 if (is_feat_mpam_supported()) { 1472 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1473 } 1474 1475 if (is_feat_fgt_supported()) { 1476 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1477 } 1478 1479 if (is_feat_fgt2_supported()) { 1480 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1481 } 1482 1483 if (is_feat_ecv_v2_supported()) { 1484 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1485 } 1486 1487 if (is_feat_vhe_supported()) { 1488 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1489 read_contextidr_el2()); 1490 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1491 } 1492 1493 if (is_feat_ras_supported()) { 1494 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1495 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1496 } 1497 1498 if (is_feat_nv2_supported()) { 1499 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1500 } 1501 1502 if (is_feat_trf_supported()) { 1503 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1504 } 1505 1506 if (is_feat_csv2_2_supported()) { 1507 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1508 read_scxtnum_el2()); 1509 } 1510 1511 if (is_feat_hcx_supported()) { 1512 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1513 } 1514 1515 if (is_feat_tcr2_supported()) { 1516 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1517 } 1518 1519 if (is_feat_sxpie_supported()) { 1520 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1521 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1522 } 1523 1524 if (is_feat_sxpoe_supported()) { 1525 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1526 } 1527 1528 if (is_feat_brbe_supported()) { 1529 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1530 } 1531 1532 if (is_feat_s2pie_supported()) { 1533 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1534 } 1535 1536 if (is_feat_gcs_supported()) { 1537 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1538 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1539 } 1540 1541 if (is_feat_sctlr2_supported()) { 1542 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1543 } 1544 } 1545 1546 /******************************************************************************* 1547 * Restore EL2 sysreg context 1548 ******************************************************************************/ 1549 void cm_el2_sysregs_context_restore(uint32_t security_state) 1550 { 1551 cpu_context_t *ctx; 1552 el2_sysregs_t *el2_sysregs_ctx; 1553 1554 ctx = cm_get_context(security_state); 1555 assert(ctx != NULL); 1556 1557 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1558 1559 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1560 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1561 1562 if (is_feat_mte2_supported()) { 1563 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1564 } 1565 1566 if (is_feat_mpam_supported()) { 1567 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1568 } 1569 1570 if (is_feat_fgt_supported()) { 1571 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1572 } 1573 1574 if (is_feat_fgt2_supported()) { 1575 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1576 } 1577 1578 if (is_feat_ecv_v2_supported()) { 1579 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1580 } 1581 1582 if (is_feat_vhe_supported()) { 1583 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1584 contextidr_el2)); 1585 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1586 } 1587 1588 if (is_feat_ras_supported()) { 1589 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1590 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1591 } 1592 1593 if (is_feat_nv2_supported()) { 1594 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1595 } 1596 1597 if (is_feat_trf_supported()) { 1598 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1599 } 1600 1601 if (is_feat_csv2_2_supported()) { 1602 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1603 scxtnum_el2)); 1604 } 1605 1606 if (is_feat_hcx_supported()) { 1607 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1608 } 1609 1610 if (is_feat_tcr2_supported()) { 1611 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1612 } 1613 1614 if (is_feat_sxpie_supported()) { 1615 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1616 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1617 } 1618 1619 if (is_feat_sxpoe_supported()) { 1620 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1621 } 1622 1623 if (is_feat_s2pie_supported()) { 1624 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1625 } 1626 1627 if (is_feat_gcs_supported()) { 1628 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1629 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1630 } 1631 1632 if (is_feat_sctlr2_supported()) { 1633 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1634 } 1635 1636 if (is_feat_brbe_supported()) { 1637 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1638 } 1639 } 1640 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1641 1642 #if IMAGE_BL31 1643 /********************************************************************************* 1644 * This function allows Architecture features asymmetry among cores. 1645 * TF-A assumes that all the cores in the platform has architecture feature parity 1646 * and hence the context is setup on different core (e.g. primary sets up the 1647 * context for secondary cores).This assumption may not be true for systems where 1648 * cores are not conforming to same Arch version or there is CPU Erratum which 1649 * requires certain feature to be be disabled only on a given core. 1650 * 1651 * This function is called on secondary cores to override any disparity in context 1652 * setup by primary, this would be called during warmboot path. 1653 *********************************************************************************/ 1654 void cm_handle_asymmetric_features(void) 1655 { 1656 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1657 1658 assert(ctx != NULL); 1659 1660 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1661 if (is_feat_spe_supported()) { 1662 spe_enable(ctx); 1663 } else { 1664 spe_disable(ctx); 1665 } 1666 #endif 1667 1668 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1669 if (check_if_affected_core() == ERRATA_APPLIES) { 1670 if (is_feat_trbe_supported()) { 1671 trbe_disable(ctx); 1672 } 1673 } 1674 #endif 1675 1676 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1677 el3_state_t *el3_state = get_el3state_ctx(ctx); 1678 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1679 1680 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1681 tcr2_enable(ctx); 1682 } else { 1683 tcr2_disable(ctx); 1684 } 1685 #endif 1686 1687 } 1688 #endif 1689 1690 /******************************************************************************* 1691 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1692 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1693 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1694 * cm_prepare_el3_exit function. 1695 ******************************************************************************/ 1696 void cm_prepare_el3_exit_ns(void) 1697 { 1698 #if IMAGE_BL31 1699 /* 1700 * Check and handle Architecture feature asymmetry among cores. 1701 * 1702 * In warmboot path secondary cores context is initialized on core which 1703 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1704 * it in this function call. 1705 * For Symmetric cores this is an empty function. 1706 */ 1707 cm_handle_asymmetric_features(); 1708 #endif 1709 1710 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1711 #if ENABLE_ASSERTIONS 1712 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1713 assert(ctx != NULL); 1714 1715 /* Assert that EL2 is used. */ 1716 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1717 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1718 (el_implemented(2U) != EL_IMPL_NONE)); 1719 #endif /* ENABLE_ASSERTIONS */ 1720 1721 /* Restore EL2 sysreg contexts */ 1722 cm_el2_sysregs_context_restore(NON_SECURE); 1723 cm_set_next_eret_context(NON_SECURE); 1724 #else 1725 cm_prepare_el3_exit(NON_SECURE); 1726 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1727 } 1728 1729 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1730 /******************************************************************************* 1731 * The next set of six functions are used by runtime services to save and restore 1732 * EL1 context on the 'cpu_context' structure for the specified security state. 1733 ******************************************************************************/ 1734 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1735 { 1736 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1737 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1738 1739 #if (!ERRATA_SPECULATIVE_AT) 1740 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1741 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1742 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1743 1744 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1745 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1746 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1747 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1748 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1749 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1750 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1751 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1752 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1753 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1754 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1755 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1756 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1757 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1758 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1759 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1760 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1761 1762 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1763 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1764 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1765 1766 if (CTX_INCLUDE_AARCH32_REGS) { 1767 /* Save Aarch32 registers */ 1768 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1769 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1770 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1771 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1772 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1773 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1774 } 1775 1776 if (NS_TIMER_SWITCH) { 1777 /* Save NS Timer registers */ 1778 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1779 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1780 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1781 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1782 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1783 } 1784 1785 if (is_feat_mte2_supported()) { 1786 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1787 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1788 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1789 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1790 } 1791 1792 if (is_feat_ras_supported()) { 1793 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1794 } 1795 1796 if (is_feat_s1pie_supported()) { 1797 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1798 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1799 } 1800 1801 if (is_feat_s1poe_supported()) { 1802 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1803 } 1804 1805 if (is_feat_s2poe_supported()) { 1806 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1807 } 1808 1809 if (is_feat_tcr2_supported()) { 1810 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1811 } 1812 1813 if (is_feat_trf_supported()) { 1814 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1815 } 1816 1817 if (is_feat_csv2_2_supported()) { 1818 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1819 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1820 } 1821 1822 if (is_feat_gcs_supported()) { 1823 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1824 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1825 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1826 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1827 } 1828 1829 if (is_feat_the_supported()) { 1830 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1831 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1832 } 1833 1834 if (is_feat_sctlr2_supported()) { 1835 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1836 } 1837 1838 if (is_feat_ls64_accdata_supported()) { 1839 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1840 } 1841 } 1842 1843 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1844 { 1845 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1846 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1847 1848 #if (!ERRATA_SPECULATIVE_AT) 1849 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1850 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1851 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1852 1853 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1854 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1855 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1856 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1857 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1858 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1859 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1860 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1861 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1862 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1863 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1864 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1865 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1866 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1867 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1868 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1869 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1870 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1871 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1872 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1873 1874 if (CTX_INCLUDE_AARCH32_REGS) { 1875 /* Restore Aarch32 registers */ 1876 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1877 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1878 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1879 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1880 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1881 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1882 } 1883 1884 if (NS_TIMER_SWITCH) { 1885 /* Restore NS Timer registers */ 1886 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1887 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1888 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1889 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1890 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1891 } 1892 1893 if (is_feat_mte2_supported()) { 1894 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1895 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1896 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1897 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1898 } 1899 1900 if (is_feat_ras_supported()) { 1901 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1902 } 1903 1904 if (is_feat_s1pie_supported()) { 1905 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1906 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1907 } 1908 1909 if (is_feat_s1poe_supported()) { 1910 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1911 } 1912 1913 if (is_feat_s2poe_supported()) { 1914 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1915 } 1916 1917 if (is_feat_tcr2_supported()) { 1918 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1919 } 1920 1921 if (is_feat_trf_supported()) { 1922 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1923 } 1924 1925 if (is_feat_csv2_2_supported()) { 1926 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1927 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1928 } 1929 1930 if (is_feat_gcs_supported()) { 1931 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1932 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1933 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1934 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1935 } 1936 1937 if (is_feat_the_supported()) { 1938 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1939 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1940 } 1941 1942 if (is_feat_sctlr2_supported()) { 1943 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1944 } 1945 1946 if (is_feat_ls64_accdata_supported()) { 1947 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1948 } 1949 } 1950 1951 /******************************************************************************* 1952 * The next couple of functions are used by runtime services to save and restore 1953 * EL1 context on the 'cpu_context' structure for the specified security state. 1954 ******************************************************************************/ 1955 void cm_el1_sysregs_context_save(uint32_t security_state) 1956 { 1957 cpu_context_t *ctx; 1958 1959 ctx = cm_get_context(security_state); 1960 assert(ctx != NULL); 1961 1962 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1963 1964 #if IMAGE_BL31 1965 if (security_state == SECURE) 1966 PUBLISH_EVENT(cm_exited_secure_world); 1967 else 1968 PUBLISH_EVENT(cm_exited_normal_world); 1969 #endif 1970 } 1971 1972 void cm_el1_sysregs_context_restore(uint32_t security_state) 1973 { 1974 cpu_context_t *ctx; 1975 1976 ctx = cm_get_context(security_state); 1977 assert(ctx != NULL); 1978 1979 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1980 1981 #if IMAGE_BL31 1982 if (security_state == SECURE) 1983 PUBLISH_EVENT(cm_entering_secure_world); 1984 else 1985 PUBLISH_EVENT(cm_entering_normal_world); 1986 #endif 1987 } 1988 1989 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1990 1991 /******************************************************************************* 1992 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1993 * given security state with the given entrypoint 1994 ******************************************************************************/ 1995 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1996 { 1997 cpu_context_t *ctx; 1998 el3_state_t *state; 1999 2000 ctx = cm_get_context(security_state); 2001 assert(ctx != NULL); 2002 2003 /* Populate EL3 state so that ERET jumps to the correct entry */ 2004 state = get_el3state_ctx(ctx); 2005 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2006 } 2007 2008 /******************************************************************************* 2009 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2010 * pertaining to the given security state 2011 ******************************************************************************/ 2012 void cm_set_elr_spsr_el3(uint32_t security_state, 2013 uintptr_t entrypoint, uint32_t spsr) 2014 { 2015 cpu_context_t *ctx; 2016 el3_state_t *state; 2017 2018 ctx = cm_get_context(security_state); 2019 assert(ctx != NULL); 2020 2021 /* Populate EL3 state so that ERET jumps to the correct entry */ 2022 state = get_el3state_ctx(ctx); 2023 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2024 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2025 } 2026 2027 /******************************************************************************* 2028 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2029 * pertaining to the given security state using the value and bit position 2030 * specified in the parameters. It preserves all other bits. 2031 ******************************************************************************/ 2032 void cm_write_scr_el3_bit(uint32_t security_state, 2033 uint32_t bit_pos, 2034 uint32_t value) 2035 { 2036 cpu_context_t *ctx; 2037 el3_state_t *state; 2038 u_register_t scr_el3; 2039 2040 ctx = cm_get_context(security_state); 2041 assert(ctx != NULL); 2042 2043 /* Ensure that the bit position is a valid one */ 2044 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2045 2046 /* Ensure that the 'value' is only a bit wide */ 2047 assert(value <= 1U); 2048 2049 /* 2050 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2051 * and set it to its new value. 2052 */ 2053 state = get_el3state_ctx(ctx); 2054 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2055 scr_el3 &= ~(1UL << bit_pos); 2056 scr_el3 |= (u_register_t)value << bit_pos; 2057 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2058 } 2059 2060 /******************************************************************************* 2061 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2062 * given security state. 2063 ******************************************************************************/ 2064 u_register_t cm_get_scr_el3(uint32_t security_state) 2065 { 2066 cpu_context_t *ctx; 2067 el3_state_t *state; 2068 2069 ctx = cm_get_context(security_state); 2070 assert(ctx != NULL); 2071 2072 /* Populate EL3 state so that ERET jumps to the correct entry */ 2073 state = get_el3state_ctx(ctx); 2074 return read_ctx_reg(state, CTX_SCR_EL3); 2075 } 2076 2077 /******************************************************************************* 2078 * This function is used to program the context that's used for exception 2079 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2080 * the required security state 2081 ******************************************************************************/ 2082 void cm_set_next_eret_context(uint32_t security_state) 2083 { 2084 cpu_context_t *ctx; 2085 2086 ctx = cm_get_context(security_state); 2087 assert(ctx != NULL); 2088 2089 cm_set_next_context(ctx); 2090 } 2091