1 /* 2 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <tools_share/uuid.h> 15 16 #include "socfpga_fcs.h" 17 #include "socfpga_mailbox.h" 18 #include "socfpga_plat_def.h" 19 #include "socfpga_reset_manager.h" 20 #include "socfpga_sip_svc.h" 21 #include "socfpga_system_manager.h" 22 23 /* Total buffer the driver can hold */ 24 #define FPGA_CONFIG_BUFFER_SIZE 4 25 26 static config_type request_type = NO_REQUEST; 27 static int current_block, current_buffer; 28 static int read_block, max_blocks; 29 static uint32_t send_id, rcv_id; 30 static uint32_t bytes_per_block, blocks_submitted; 31 static bool bridge_disable; 32 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 33 static uint32_t g_remapper_bypass; 34 #endif 35 36 /* RSU static variables */ 37 static uint32_t rsu_dcmf_ver[4] = {0}; 38 static uint16_t rsu_dcmf_stat[4] = {0}; 39 static uint32_t rsu_max_retry; 40 41 /* SiP Service UUID */ 42 DEFINE_SVC_UUID2(intl_svc_uid, 43 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 44 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 45 46 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 47 uint64_t x1, 48 uint64_t x2, 49 uint64_t x3, 50 uint64_t x4, 51 void *cookie, 52 void *handle, 53 uint64_t flags) 54 { 55 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 56 SMC_RET1(handle, SMC_UNK); 57 } 58 59 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 60 61 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 62 { 63 uint32_t args[3]; 64 65 while (max_blocks > 0 && buffer->size > buffer->size_written) { 66 args[0] = (1<<8); 67 args[1] = buffer->addr + buffer->size_written; 68 if (buffer->size - buffer->size_written <= bytes_per_block) { 69 args[2] = buffer->size - buffer->size_written; 70 current_buffer++; 71 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 72 } else { 73 args[2] = bytes_per_block; 74 } 75 76 buffer->size_written += args[2]; 77 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 78 3U, CMD_INDIRECT); 79 80 buffer->subblocks_sent++; 81 max_blocks--; 82 } 83 84 return !max_blocks; 85 } 86 87 static int intel_fpga_sdm_write_all(void) 88 { 89 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 90 if (intel_fpga_sdm_write_buffer( 91 &fpga_config_buffers[current_buffer])) { 92 break; 93 } 94 } 95 return 0; 96 } 97 98 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 99 { 100 uint32_t ret; 101 102 if (err_states == NULL) 103 return INTEL_SIP_SMC_STATUS_REJECTED; 104 105 switch (request_type) { 106 case RECONFIGURATION: 107 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 108 true, err_states); 109 break; 110 case BITSTREAM_AUTH: 111 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 112 false, err_states); 113 break; 114 default: 115 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 116 false, err_states); 117 break; 118 } 119 120 if (ret != 0U) { 121 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 122 return INTEL_SIP_SMC_STATUS_BUSY; 123 } else { 124 request_type = NO_REQUEST; 125 return INTEL_SIP_SMC_STATUS_ERROR; 126 } 127 } 128 129 if (bridge_disable != 0U) { 130 socfpga_bridges_enable(~0); /* Enable bridge */ 131 bridge_disable = false; 132 } 133 request_type = NO_REQUEST; 134 135 return INTEL_SIP_SMC_STATUS_OK; 136 } 137 138 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 139 { 140 int i; 141 142 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 143 if (fpga_config_buffers[i].block_number == current_block) { 144 fpga_config_buffers[i].subblocks_sent--; 145 if (fpga_config_buffers[i].subblocks_sent == 0 146 && fpga_config_buffers[i].size <= 147 fpga_config_buffers[i].size_written) { 148 fpga_config_buffers[i].write_requested = 0; 149 current_block++; 150 *buffer_addr_completed = 151 fpga_config_buffers[i].addr; 152 return 0; 153 } 154 } 155 } 156 157 return -1; 158 } 159 160 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 161 uint32_t *count, uint32_t *job_id) 162 { 163 uint32_t resp[5]; 164 unsigned int resp_len = ARRAY_SIZE(resp); 165 int status = INTEL_SIP_SMC_STATUS_OK; 166 int all_completed = 1; 167 *count = 0; 168 169 while (*count < 3) { 170 171 status = mailbox_read_response(job_id, 172 resp, &resp_len); 173 174 if (status < 0) { 175 break; 176 } 177 178 max_blocks++; 179 180 if (mark_last_buffer_xfer_completed( 181 &completed_addr[*count]) == 0) { 182 *count = *count + 1; 183 } else { 184 break; 185 } 186 } 187 188 if (*count <= 0) { 189 if (status != MBOX_NO_RESPONSE && 190 status != MBOX_TIMEOUT && resp_len != 0) { 191 mailbox_clear_response(); 192 request_type = NO_REQUEST; 193 return INTEL_SIP_SMC_STATUS_ERROR; 194 } 195 196 *count = 0; 197 } 198 199 intel_fpga_sdm_write_all(); 200 201 if (*count > 0) { 202 status = INTEL_SIP_SMC_STATUS_OK; 203 } else if (*count == 0) { 204 status = INTEL_SIP_SMC_STATUS_BUSY; 205 } 206 207 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 208 if (fpga_config_buffers[i].write_requested != 0) { 209 all_completed = 0; 210 break; 211 } 212 } 213 214 if (all_completed == 1) { 215 return INTEL_SIP_SMC_STATUS_OK; 216 } 217 218 return status; 219 } 220 221 static int intel_fpga_config_start(uint32_t flag) 222 { 223 uint32_t argument = 0x1; 224 uint32_t response[3]; 225 int status = 0; 226 unsigned int size = 0; 227 unsigned int resp_len = ARRAY_SIZE(response); 228 229 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 230 /* 231 * To trigger isolation 232 * FPGA configuration complete signal should be de-asserted 233 */ 234 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 235 status = mailbox_send_fpga_config_comp(); 236 237 if (status < 0) { 238 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 239 } 240 #endif 241 242 request_type = RECONFIGURATION; 243 244 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 245 bridge_disable = true; 246 } 247 248 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 249 size = 1; 250 bridge_disable = false; 251 request_type = BITSTREAM_AUTH; 252 } 253 254 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 255 intel_smmu_hps_remapper_init(0U); 256 #endif 257 258 mailbox_clear_response(); 259 260 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 261 CMD_CASUAL, NULL, NULL); 262 263 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 264 CMD_CASUAL, response, &resp_len); 265 266 if (status < 0) { 267 bridge_disable = false; 268 request_type = NO_REQUEST; 269 return INTEL_SIP_SMC_STATUS_ERROR; 270 } 271 272 max_blocks = response[0]; 273 bytes_per_block = response[1]; 274 275 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 276 fpga_config_buffers[i].size = 0; 277 fpga_config_buffers[i].size_written = 0; 278 fpga_config_buffers[i].addr = 0; 279 fpga_config_buffers[i].write_requested = 0; 280 fpga_config_buffers[i].block_number = 0; 281 fpga_config_buffers[i].subblocks_sent = 0; 282 } 283 284 blocks_submitted = 0; 285 current_block = 0; 286 read_block = 0; 287 current_buffer = 0; 288 289 /* Disable bridge on full reconfiguration */ 290 if (bridge_disable) { 291 socfpga_bridges_disable(~0); 292 } 293 294 return INTEL_SIP_SMC_STATUS_OK; 295 } 296 297 static bool is_fpga_config_buffer_full(void) 298 { 299 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 300 if (!fpga_config_buffers[i].write_requested) { 301 return false; 302 } 303 } 304 return true; 305 } 306 307 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 308 { 309 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 310 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 311 312 if (!addr && !size) { 313 return true; 314 } 315 if (size > (UINT64_MAX - addr)) { 316 return false; 317 } 318 if (addr < BL31_LIMIT) { 319 return false; 320 } 321 if (dram_region_end > dram_max_sz) { 322 return false; 323 } 324 325 return true; 326 } 327 328 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 329 { 330 int i; 331 332 intel_fpga_sdm_write_all(); 333 334 if (!is_address_in_ddr_range(mem, size) || 335 is_fpga_config_buffer_full()) { 336 return INTEL_SIP_SMC_STATUS_REJECTED; 337 } 338 339 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 340 intel_smmu_hps_remapper_init(&mem); 341 #endif 342 343 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 344 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 345 346 if (!fpga_config_buffers[j].write_requested) { 347 fpga_config_buffers[j].addr = mem; 348 fpga_config_buffers[j].size = size; 349 fpga_config_buffers[j].size_written = 0; 350 fpga_config_buffers[j].write_requested = 1; 351 fpga_config_buffers[j].block_number = 352 blocks_submitted++; 353 fpga_config_buffers[j].subblocks_sent = 0; 354 break; 355 } 356 } 357 358 if (is_fpga_config_buffer_full()) { 359 return INTEL_SIP_SMC_STATUS_BUSY; 360 } 361 362 return INTEL_SIP_SMC_STATUS_OK; 363 } 364 365 static int is_out_of_sec_range(uint64_t reg_addr) 366 { 367 #if DEBUG 368 return 0; 369 #endif 370 371 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 372 switch (reg_addr) { 373 case(0xF8011100): /* ECCCTRL1 */ 374 case(0xF8011104): /* ECCCTRL2 */ 375 case(0xF8011110): /* ERRINTEN */ 376 case(0xF8011114): /* ERRINTENS */ 377 case(0xF8011118): /* ERRINTENR */ 378 case(0xF801111C): /* INTMODE */ 379 case(0xF8011120): /* INTSTAT */ 380 case(0xF8011124): /* DIAGINTTEST */ 381 case(0xF801112C): /* DERRADDRA */ 382 case(0xFA000000): /* SMMU SCR0 */ 383 case(0xFA000004): /* SMMU SCR1 */ 384 case(0xFA000400): /* SMMU NSCR0 */ 385 case(0xFA004000): /* SMMU SSD0_REG */ 386 case(0xFA000820): /* SMMU SMR8 */ 387 case(0xFA000c20): /* SMMU SCR8 */ 388 case(0xFA028000): /* SMMU CB8_SCTRL */ 389 case(0xFA001020): /* SMMU CBAR8 */ 390 case(0xFA028030): /* SMMU TCR_LPAE */ 391 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 392 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 393 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 394 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 395 case(0xFA028010): /* SMMU_CB8)TCR2 */ 396 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 397 case(0xFA001820): /* SMMU_CBA2R8 */ 398 case(0xFA000074): /* SMMU_STLBGSTATUS */ 399 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 400 case(0xFA000060): /* SMMU_STLBIALL */ 401 case(0xFA000070): /* SMMU_STLBGSYNC */ 402 case(0xFA028618): /* CB8_TLBALL */ 403 case(0xFA0287F0): /* CB8_TLBSYNC */ 404 case(0xFFD12028): /* SDMMCGRP_CTRL */ 405 case(0xFFD12044): /* EMAC0 */ 406 case(0xFFD12048): /* EMAC1 */ 407 case(0xFFD1204C): /* EMAC2 */ 408 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 409 case(0xFFD12094): /* ECC_INT_MASK_SET */ 410 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 411 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 412 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 413 case(0xFFD120C0): /* NOC_TIMEOUT */ 414 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 415 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 416 case(0xFFD120D0): /* NOC_IDLEACK */ 417 case(0xFFD120D4): /* NOC_IDLESTATUS */ 418 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 419 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 420 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 421 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 422 return 0; 423 #else 424 switch (reg_addr) { 425 426 case(0xF8011104): /* ECCCTRL2 */ 427 case(0xFFD12028): /* SDMMCGRP_CTRL */ 428 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 429 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 430 case(0xFFD120D0): /* NOC_IDLEACK */ 431 432 433 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 434 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 435 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 436 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 437 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 438 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 439 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 440 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 441 442 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 443 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 444 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 445 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 450 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 451 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 452 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 456 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 457 #endif 458 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 459 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 461 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 462 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 463 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 464 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 465 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 466 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 467 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 468 return 0; 469 470 default: 471 break; 472 } 473 474 return -1; 475 } 476 477 /* Secure register access */ 478 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 479 { 480 if (is_out_of_sec_range(reg_addr)) { 481 return INTEL_SIP_SMC_STATUS_ERROR; 482 } 483 484 *retval = mmio_read_32(reg_addr); 485 486 return INTEL_SIP_SMC_STATUS_OK; 487 } 488 489 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 490 uint32_t *retval) 491 { 492 if (is_out_of_sec_range(reg_addr)) { 493 return INTEL_SIP_SMC_STATUS_ERROR; 494 } 495 496 switch (reg_addr) { 497 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 498 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 499 mmio_write_16(reg_addr, val); 500 break; 501 default: 502 mmio_write_32(reg_addr, val); 503 break; 504 } 505 506 return intel_secure_reg_read(reg_addr, retval); 507 } 508 509 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 510 uint32_t val, uint32_t *retval) 511 { 512 if (!intel_secure_reg_read(reg_addr, retval)) { 513 *retval &= ~mask; 514 *retval |= val & mask; 515 return intel_secure_reg_write(reg_addr, *retval, retval); 516 } 517 518 return INTEL_SIP_SMC_STATUS_ERROR; 519 } 520 521 /* Intel Remote System Update (RSU) services */ 522 uint64_t intel_rsu_update_address; 523 524 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 525 { 526 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 527 return INTEL_SIP_SMC_RSU_ERROR; 528 } 529 530 return INTEL_SIP_SMC_STATUS_OK; 531 } 532 533 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 534 unsigned int respbuf_sz) 535 { 536 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 537 return INTEL_SIP_SMC_RSU_ERROR; 538 } 539 540 return INTEL_SIP_SMC_STATUS_OK; 541 } 542 543 uint32_t intel_rsu_update(uint64_t update_address) 544 { 545 if (update_address > SIZE_MAX) { 546 return INTEL_SIP_SMC_STATUS_REJECTED; 547 } 548 549 intel_rsu_update_address = update_address; 550 return INTEL_SIP_SMC_STATUS_OK; 551 } 552 553 static uint32_t intel_rsu_notify(uint32_t execution_stage) 554 { 555 if (mailbox_hps_stage_notify(execution_stage) < 0) { 556 return INTEL_SIP_SMC_RSU_ERROR; 557 } 558 559 return INTEL_SIP_SMC_STATUS_OK; 560 } 561 562 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 563 uint32_t *ret_stat) 564 { 565 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 566 return INTEL_SIP_SMC_RSU_ERROR; 567 } 568 569 *ret_stat = respbuf[8]; 570 return INTEL_SIP_SMC_STATUS_OK; 571 } 572 573 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 574 uint64_t dcmf_ver_3_2) 575 { 576 rsu_dcmf_ver[0] = dcmf_ver_1_0; 577 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 578 rsu_dcmf_ver[2] = dcmf_ver_3_2; 579 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 580 581 return INTEL_SIP_SMC_STATUS_OK; 582 } 583 584 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 585 { 586 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 587 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 588 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 589 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 590 591 return INTEL_SIP_SMC_STATUS_OK; 592 } 593 594 /* Intel HWMON services */ 595 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 596 { 597 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 598 return INTEL_SIP_SMC_STATUS_ERROR; 599 } 600 601 return INTEL_SIP_SMC_STATUS_OK; 602 } 603 604 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 605 { 606 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 607 return INTEL_SIP_SMC_STATUS_ERROR; 608 } 609 610 return INTEL_SIP_SMC_STATUS_OK; 611 } 612 613 /* Mailbox services */ 614 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 615 { 616 int status; 617 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 618 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 619 620 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 621 CMD_CASUAL, resp_data, &resp_len); 622 623 if (status < 0) { 624 return INTEL_SIP_SMC_STATUS_ERROR; 625 } 626 627 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 628 return INTEL_SIP_SMC_STATUS_ERROR; 629 } 630 631 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 632 633 return INTEL_SIP_SMC_STATUS_OK; 634 } 635 636 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 637 unsigned int len, uint32_t urgent, uint64_t response, 638 unsigned int resp_len, int *mbox_status, 639 unsigned int *len_in_resp) 640 { 641 *len_in_resp = 0; 642 *mbox_status = GENERIC_RESPONSE_ERROR; 643 644 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 645 return INTEL_SIP_SMC_STATUS_REJECTED; 646 } 647 648 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 649 (uint32_t *) response, &resp_len); 650 651 if (status < 0) { 652 *mbox_status = -status; 653 return INTEL_SIP_SMC_STATUS_ERROR; 654 } 655 656 *mbox_status = 0; 657 *len_in_resp = resp_len; 658 659 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 660 661 return INTEL_SIP_SMC_STATUS_OK; 662 } 663 664 static int intel_smc_get_usercode(uint32_t *user_code) 665 { 666 int status; 667 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 668 669 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 670 0U, CMD_CASUAL, user_code, &resp_len); 671 672 if (status < 0) { 673 return INTEL_SIP_SMC_STATUS_ERROR; 674 } 675 676 return INTEL_SIP_SMC_STATUS_OK; 677 } 678 679 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 680 uint32_t mode, uint32_t *job_id, 681 uint32_t *ret_size, uint32_t *mbox_error) 682 { 683 int status = 0; 684 uint32_t resp_len = size / MBOX_WORD_BYTE; 685 686 if (resp_len > MBOX_DATA_MAX_LEN) { 687 return INTEL_SIP_SMC_STATUS_REJECTED; 688 } 689 690 if (!is_address_in_ddr_range(addr, size)) { 691 return INTEL_SIP_SMC_STATUS_REJECTED; 692 } 693 694 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 695 status = mailbox_read_response_async(job_id, 696 NULL, (uint32_t *) addr, &resp_len, 0); 697 } else { 698 status = mailbox_read_response(job_id, 699 (uint32_t *) addr, &resp_len); 700 701 if (status == MBOX_NO_RESPONSE) { 702 status = MBOX_BUSY; 703 } 704 } 705 706 if (status == MBOX_NO_RESPONSE) { 707 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 708 } 709 710 if (status == MBOX_BUSY) { 711 return INTEL_SIP_SMC_STATUS_BUSY; 712 } 713 714 *ret_size = resp_len * MBOX_WORD_BYTE; 715 flush_dcache_range(addr, *ret_size); 716 717 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 718 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 719 *mbox_error = -status; 720 } else if (status != MBOX_RET_OK) { 721 *mbox_error = -status; 722 return INTEL_SIP_SMC_STATUS_ERROR; 723 } 724 725 return INTEL_SIP_SMC_STATUS_OK; 726 } 727 728 /* Miscellaneous HPS services */ 729 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 730 { 731 int status = 0; 732 733 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 734 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 735 status = socfpga_bridges_enable((uint32_t)mask); 736 } else { 737 status = socfpga_bridges_enable(~0); 738 } 739 } else { 740 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 741 status = socfpga_bridges_disable((uint32_t)mask); 742 } else { 743 status = socfpga_bridges_disable(~0); 744 } 745 } 746 747 if (status < 0) { 748 return INTEL_SIP_SMC_STATUS_ERROR; 749 } 750 751 return INTEL_SIP_SMC_STATUS_OK; 752 } 753 754 /* SDM SEU Error services */ 755 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 756 { 757 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 758 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 759 } 760 761 return INTEL_SIP_SMC_STATUS_OK; 762 } 763 764 /* SDM SAFE SEU Error inject services */ 765 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 766 { 767 if (mailbox_safe_inject_seu_err(command, len) < 0) { 768 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 769 } 770 771 return INTEL_SIP_SMC_STATUS_OK; 772 } 773 774 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 775 /* SMMU HPS Remapper */ 776 void intel_smmu_hps_remapper_init(uint64_t *mem) 777 { 778 /* Read out Bit 1 value */ 779 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 780 781 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 782 /* Update DRAM Base address for SDM SMMU */ 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 784 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 785 *mem = *mem - DRAM_BASE; 786 } else { 787 *mem = *mem - DRAM_BASE; 788 } 789 } 790 791 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 792 { 793 /* Read out the JTAG-ID from boot scratch register */ 794 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 795 if (remapper_bypass == 0x01) { 796 g_remapper_bypass = remapper_bypass; 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 798 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 799 } 800 } 801 return INTEL_SIP_SMC_STATUS_OK; 802 } 803 804 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 805 { 806 volatile uint64_t atf_ddr_buffer; 807 volatile uint64_t val; 808 809 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 810 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 811 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 812 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 813 memcpy_s((void *)&val, sizeof(val), 814 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 815 816 /* Clear response_ready BIT0 of status_register before sending next command. */ 817 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 818 } 819 #endif 820 821 #if SIP_SVC_V3 822 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 823 { 824 uint8_t ret_args_len = 0U; 825 sdm_response_t *resp = (sdm_response_t *)resp_desc; 826 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 827 828 (void)cmd; 829 /* Returns 3 SMC arguments for SMC_RET3 */ 830 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 831 ret_args[ret_args_len++] = resp->err_code; 832 833 return ret_args_len; 834 } 835 836 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 837 { 838 uint8_t ret_args_len = 0U; 839 sdm_response_t *resp = (sdm_response_t *)resp_desc; 840 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 841 842 (void)cmd; 843 /* Returns 3 SMC arguments for SMC_RET3 */ 844 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 845 ret_args[ret_args_len++] = resp->err_code; 846 ret_args[ret_args_len++] = resp->resp_data[0]; 847 848 return ret_args_len; 849 } 850 851 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 852 { 853 uint8_t ret_args_len = 0U; 854 sdm_response_t *resp = (sdm_response_t *)resp_desc; 855 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 856 857 (void)cmd; 858 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 859 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 860 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 864 865 return ret_args_len; 866 } 867 868 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 869 { 870 uint8_t ret_args_len = 0U; 871 sdm_response_t *resp = (sdm_response_t *)resp_desc; 872 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 873 874 (void)cmd; 875 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 876 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 877 878 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 879 ret_args[ret_args_len++] = resp->err_code; 880 ret_args[ret_args_len++] = resp->resp_data[0]; 881 ret_args[ret_args_len++] = resp->resp_data[1]; 882 883 return ret_args_len; 884 } 885 886 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 887 { 888 uint8_t ret_args_len = 0U; 889 uint32_t retry_counter = ~0U; 890 uint32_t failure_source = 0U; 891 sdm_response_t *resp = (sdm_response_t *)resp_desc; 892 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 893 894 (void)cmd; 895 /* Get the failure source and current image retry counter value from the response. */ 896 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK; 897 retry_counter = resp->resp_data[8]; 898 899 if ((retry_counter != ~0U) && (failure_source == 0U)) 900 resp->resp_data[5] |= RSU_VERSION_ACMF; 901 902 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 903 ret_args[ret_args_len++] = resp->err_code; 904 /* Current CMF */ 905 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]); 906 /* Last Failing CMF Address */ 907 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]); 908 /* Config State */ 909 ret_args[ret_args_len++] = resp->resp_data[4]; 910 /* Version */ 911 ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]); 912 /* Failure Source */ 913 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16); 914 /* Error location */ 915 ret_args[ret_args_len++] = resp->resp_data[6]; 916 /* Error details */ 917 ret_args[ret_args_len++] = resp->resp_data[7]; 918 /* Current image retry counter */ 919 ret_args[ret_args_len++] = resp->resp_data[8]; 920 921 return ret_args_len; 922 } 923 924 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 925 { 926 uint8_t ret_args_len = 0U; 927 sdm_response_t *resp = (sdm_response_t *)resp_desc; 928 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 929 930 (void)cmd; 931 932 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 933 ret_args[ret_args_len++] = resp->err_code; 934 /* Sub Partition Table (SPT) 0 address */ 935 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]); 936 /* Sub Partition Table (SPT) 1 address */ 937 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]); 938 939 return ret_args_len; 940 } 941 942 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 943 { 944 945 switch (ret_args_len) { 946 case SMC_RET_ARGS_ONE: 947 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 948 SMC_RET1(handle, ret_args[0]); 949 break; 950 951 case SMC_RET_ARGS_TWO: 952 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 953 SMC_RET2(handle, ret_args[0], ret_args[1]); 954 break; 955 956 case SMC_RET_ARGS_THREE: 957 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 958 __func__, ret_args[0], ret_args[1], ret_args[2]); 959 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 960 break; 961 962 case SMC_RET_ARGS_FOUR: 963 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 964 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 965 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 966 break; 967 968 case SMC_RET_ARGS_FIVE: 969 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 970 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 971 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 972 break; 973 974 case SMC_RET_ARGS_SIX: 975 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 976 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 977 ret_args[5]); 978 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 979 ret_args[5]); 980 break; 981 982 case SMC_RET_ARGS_SEVEN: 983 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 984 "x6 0x%lx\n", 985 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 986 ret_args[5], ret_args[6]); 987 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 988 ret_args[5], ret_args[6]); 989 break; 990 991 case SMC_RET_ARGS_EIGHT: 992 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 993 "x6 0x%lx, x7 0x%lx\n", 994 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 995 ret_args[5], ret_args[6], ret_args[7]); 996 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 997 ret_args[5], ret_args[6], ret_args[7]); 998 break; 999 1000 case SMC_RET_ARGS_NINE: 1001 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1002 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 1003 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1004 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 1005 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1006 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1007 0, 0, 0, 0, 0, 0, 0, 0, 0); 1008 break; 1009 1010 case SMC_RET_ARGS_TEN: 1011 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1012 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 1013 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 1014 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1015 ret_args[9], ret_args[10]); 1016 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1017 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 1018 0, 0, 0, 0, 0, 0, 0, 0); 1019 break; 1020 1021 default: 1022 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 1023 __func__, ret_args_len); 1024 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1025 break; 1026 } 1027 } 1028 1029 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 1030 { 1031 /* Check if the command is allowed to be executed in generic mbox format */ 1032 bool is_cmd_allowed = false; 1033 1034 switch (cmd) { 1035 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1036 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1037 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1038 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1039 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1040 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1041 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1042 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1043 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1044 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1045 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1046 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1047 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1048 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1049 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1050 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1051 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1052 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1053 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1054 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1055 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1056 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1057 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1058 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1059 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1060 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1061 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1062 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1063 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1064 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1065 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1066 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1067 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1068 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1069 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION: 1070 /* These commands are not supported in the generic mailbox format. */ 1071 break; 1072 1073 default: 1074 is_cmd_allowed = true; 1075 break; 1076 } /* switch */ 1077 1078 return is_cmd_allowed; 1079 } 1080 1081 /* 1082 * This function is responsible for handling all SiP SVC V3 calls from the 1083 * non-secure world. 1084 */ 1085 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1086 u_register_t x1, 1087 u_register_t x2, 1088 u_register_t x3, 1089 u_register_t x4, 1090 void *cookie, 1091 void *handle, 1092 u_register_t flags) 1093 { 1094 int status = 0; 1095 uint32_t mbox_error = 0U; 1096 u_register_t x5, x6, x7, x8, x9, x10, x11; 1097 1098 /* Get all the SMC call arguments */ 1099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1100 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1101 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1102 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1103 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1104 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1105 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1106 1107 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1108 smc_fid, x1, x2, x3, x4, x5); 1109 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1110 x6, x7, x8, x9, x10, x11); 1111 1112 switch (smc_fid) { 1113 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1114 { 1115 uint64_t ret_args[16] = {0}; 1116 uint32_t ret_args_len = 0; 1117 1118 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1119 GET_JOB_ID(x1), 1120 ret_args, 1121 &ret_args_len); 1122 /* Always reserve [0] index for command status. */ 1123 ret_args[0] = status; 1124 1125 /* Return SMC call based on the number of return arguments */ 1126 return smc_ret(handle, ret_args, ret_args_len); 1127 } 1128 1129 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1130 { 1131 /* TBD: Here now we don't need these CID and JID?? */ 1132 uint8_t client_id = 0U; 1133 uint8_t job_id = 0U; 1134 uint64_t trans_id_bitmap[4] = {0U}; 1135 1136 status = mailbox_response_poll_on_intr_v3(&client_id, 1137 &job_id, 1138 trans_id_bitmap); 1139 1140 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1141 trans_id_bitmap[2], trans_id_bitmap[3]); 1142 break; 1143 } 1144 1145 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1146 { 1147 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1148 GET_JOB_ID(x1), 1149 MBOX_CMD_GET_DEVICEID, 1150 NULL, 1151 0U, 1152 MBOX_CMD_FLAG_CASUAL, 1153 sip_smc_ret_nbytes_cb, 1154 (uint32_t *)x2, 1155 2); 1156 1157 SMC_RET1(handle, status); 1158 } 1159 1160 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1161 { 1162 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1163 GET_JOB_ID(x1), 1164 MBOX_CMD_GET_IDCODE, 1165 NULL, 1166 0U, 1167 MBOX_CMD_FLAG_CASUAL, 1168 sip_smc_cmd_cb_ret3, 1169 NULL, 1170 0); 1171 1172 SMC_RET1(handle, status); 1173 } 1174 1175 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1176 { 1177 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1178 GET_JOB_ID(x1), 1179 MBOX_CMD_QSPI_OPEN, 1180 NULL, 1181 0U, 1182 MBOX_CMD_FLAG_CASUAL, 1183 sip_smc_cmd_cb_ret2, 1184 NULL, 1185 0U); 1186 1187 SMC_RET1(handle, status); 1188 } 1189 1190 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1191 { 1192 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1193 GET_JOB_ID(x1), 1194 MBOX_CMD_QSPI_CLOSE, 1195 NULL, 1196 0U, 1197 MBOX_CMD_FLAG_CASUAL, 1198 sip_smc_cmd_cb_ret2, 1199 NULL, 1200 0U); 1201 1202 SMC_RET1(handle, status); 1203 } 1204 1205 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1206 { 1207 uint32_t cmd_data = 0U; 1208 uint32_t chip_sel = (uint32_t)x2; 1209 uint32_t comb_addr_mode = (uint32_t)x3; 1210 uint32_t ext_dec_mode = (uint32_t)x4; 1211 1212 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1213 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1214 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1215 1216 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1217 GET_JOB_ID(x1), 1218 MBOX_CMD_QSPI_SET_CS, 1219 &cmd_data, 1220 1U, 1221 MBOX_CMD_FLAG_CASUAL, 1222 sip_smc_cmd_cb_ret2, 1223 NULL, 1224 0U); 1225 1226 SMC_RET1(handle, status); 1227 } 1228 1229 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1230 { 1231 uint32_t qspi_addr = (uint32_t)x2; 1232 uint32_t qspi_nwords = (uint32_t)x3; 1233 1234 /* QSPI address offset to start erase, must be 4K aligned */ 1235 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1236 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1237 smc_fid); 1238 status = INTEL_SIP_SMC_STATUS_REJECTED; 1239 SMC_RET1(handle, status); 1240 } 1241 1242 /* Number of words to erase, multiples of 0x400 or 4K */ 1243 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1244 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1245 smc_fid); 1246 status = INTEL_SIP_SMC_STATUS_REJECTED; 1247 SMC_RET1(handle, status); 1248 } 1249 1250 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1251 1252 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1253 GET_JOB_ID(x1), 1254 MBOX_CMD_QSPI_ERASE, 1255 cmd_data, 1256 sizeof(cmd_data) / MBOX_WORD_BYTE, 1257 MBOX_CMD_FLAG_CASUAL, 1258 sip_smc_cmd_cb_ret2, 1259 NULL, 1260 0U); 1261 1262 SMC_RET1(handle, status); 1263 } 1264 1265 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1266 { 1267 uint32_t *qspi_payload = (uint32_t *)x2; 1268 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1269 uint32_t qspi_addr = qspi_payload[0]; 1270 uint32_t qspi_nwords = qspi_payload[1]; 1271 1272 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1273 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1274 smc_fid); 1275 status = INTEL_SIP_SMC_STATUS_REJECTED; 1276 SMC_RET1(handle, status); 1277 } 1278 1279 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1280 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1281 smc_fid); 1282 status = INTEL_SIP_SMC_STATUS_REJECTED; 1283 SMC_RET1(handle, status); 1284 } 1285 1286 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1287 GET_JOB_ID(x1), 1288 MBOX_CMD_QSPI_WRITE, 1289 qspi_payload, 1290 qspi_total_nwords, 1291 MBOX_CMD_FLAG_CASUAL, 1292 sip_smc_cmd_cb_ret2, 1293 NULL, 1294 0U); 1295 1296 SMC_RET1(handle, status); 1297 } 1298 1299 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1300 { 1301 uint32_t qspi_addr = (uint32_t)x2; 1302 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1303 1304 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1305 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1306 smc_fid); 1307 status = INTEL_SIP_SMC_STATUS_REJECTED; 1308 SMC_RET1(handle, status); 1309 } 1310 1311 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1312 1313 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1314 GET_JOB_ID(x1), 1315 MBOX_CMD_QSPI_READ, 1316 cmd_data, 1317 sizeof(cmd_data) / MBOX_WORD_BYTE, 1318 MBOX_CMD_FLAG_CASUAL, 1319 sip_smc_ret_nbytes_cb, 1320 (uint32_t *)x3, 1321 2); 1322 1323 SMC_RET1(handle, status); 1324 } 1325 1326 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1327 { 1328 uint32_t *dst_addr = (uint32_t *)x2; 1329 1330 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1331 GET_JOB_ID(x1), 1332 MBOX_CMD_QSPI_GET_DEV_INFO, 1333 NULL, 1334 0U, 1335 MBOX_CMD_FLAG_CASUAL, 1336 sip_smc_ret_nbytes_cb, 1337 (uint32_t *)dst_addr, 1338 2); 1339 1340 SMC_RET1(handle, status); 1341 } 1342 1343 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1344 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1345 { 1346 uint32_t channel = (uint32_t)x2; 1347 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1348 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1349 1350 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1351 GET_JOB_ID(x1), 1352 mbox_cmd, 1353 &channel, 1354 1U, 1355 MBOX_CMD_FLAG_CASUAL, 1356 sip_smc_cmd_cb_ret3, 1357 NULL, 1358 0); 1359 1360 SMC_RET1(handle, status); 1361 } 1362 1363 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT: 1364 { 1365 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1366 GET_JOB_ID(x1), 1367 MBOX_GET_SUBPARTITION_TABLE, 1368 NULL, 1369 0, 1370 MBOX_CMD_FLAG_CASUAL, 1371 sip_smc_cmd_cb_rsu_spt, 1372 NULL, 1373 0); 1374 1375 SMC_RET1(handle, status); 1376 } 1377 1378 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS: 1379 { 1380 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1381 GET_JOB_ID(x1), 1382 MBOX_RSU_STATUS, 1383 NULL, 1384 0, 1385 MBOX_CMD_FLAG_CASUAL, 1386 sip_smc_cmd_cb_rsu_status, 1387 NULL, 1388 0); 1389 1390 SMC_RET1(handle, status); 1391 } 1392 1393 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY: 1394 { 1395 uint32_t notify_code = (uint32_t)x2; 1396 1397 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1398 GET_JOB_ID(x1), 1399 MBOX_HPS_STAGE_NOTIFY, 1400 ¬ify_code, 1401 1U, 1402 MBOX_CMD_FLAG_CASUAL, 1403 sip_smc_cmd_cb_ret2, 1404 NULL, 1405 0); 1406 1407 SMC_RET1(handle, status); 1408 } 1409 1410 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1411 { 1412 /* Filter the required commands here. */ 1413 if (!is_gen_mbox_cmd_allowed(smc_fid)) { 1414 status = INTEL_SIP_SMC_STATUS_REJECTED; 1415 SMC_RET1(handle, status); 1416 } 1417 1418 /* Collect all the args passed in, and send the mailbox command. */ 1419 uint32_t mbox_cmd = (uint32_t)x2; 1420 uint32_t *cmd_payload_addr = NULL; 1421 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1422 uint32_t *resp_payload_addr = NULL; 1423 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1424 1425 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1426 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1427 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1428 smc_fid); 1429 status = INTEL_SIP_SMC_STATUS_REJECTED; 1430 SMC_RET1(handle, status); 1431 } 1432 1433 /* Make sure we have valid command payload length and buffer */ 1434 if (cmd_payload_len != 0U) { 1435 cmd_payload_addr = (uint32_t *)x3; 1436 if (cmd_payload_addr == NULL) { 1437 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1438 smc_fid); 1439 status = INTEL_SIP_SMC_STATUS_REJECTED; 1440 SMC_RET1(handle, status); 1441 } 1442 } 1443 1444 /* Make sure we have valid response payload length and buffer */ 1445 if (resp_payload_len != 0U) { 1446 resp_payload_addr = (uint32_t *)x5; 1447 if (resp_payload_addr == NULL) { 1448 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1449 smc_fid); 1450 status = INTEL_SIP_SMC_STATUS_REJECTED; 1451 SMC_RET1(handle, status); 1452 } 1453 } 1454 1455 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1456 GET_JOB_ID(x1), 1457 mbox_cmd, 1458 (uint32_t *)cmd_payload_addr, 1459 cmd_payload_len, 1460 MBOX_CMD_FLAG_CASUAL, 1461 sip_smc_ret_nbytes_cb, 1462 (uint32_t *)resp_payload_addr, 1463 resp_payload_len); 1464 1465 SMC_RET1(handle, status); 1466 } 1467 1468 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1469 { 1470 uint32_t session_id = (uint32_t)x2; 1471 uint32_t context_id = (uint32_t)x3; 1472 uint64_t ret_random_addr = (uint64_t)x4; 1473 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1474 uint32_t crypto_header = 0U; 1475 1476 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1477 (random_len == 0U) || 1478 (!is_size_4_bytes_aligned(random_len))) { 1479 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1480 status = INTEL_SIP_SMC_STATUS_REJECTED; 1481 SMC_RET1(handle, status); 1482 } 1483 1484 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1485 FCS_CS_FIELD_FLAG_OFFSET); 1486 fcs_rng_payload payload = {session_id, context_id, 1487 crypto_header, random_len}; 1488 1489 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1490 GET_JOB_ID(x1), 1491 MBOX_FCS_RANDOM_GEN, 1492 (uint32_t *)&payload, 1493 sizeof(payload) / MBOX_WORD_BYTE, 1494 MBOX_CMD_FLAG_CASUAL, 1495 sip_smc_ret_nbytes_cb, 1496 (uint32_t *)ret_random_addr, 1497 2); 1498 SMC_RET1(handle, status); 1499 } 1500 1501 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1502 { 1503 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1504 GET_JOB_ID(x1), 1505 MBOX_FCS_GET_PROVISION, 1506 NULL, 1507 0U, 1508 MBOX_CMD_FLAG_CASUAL, 1509 sip_smc_ret_nbytes_cb, 1510 (uint32_t *)x2, 1511 2); 1512 SMC_RET1(handle, status); 1513 } 1514 1515 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1516 { 1517 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1518 x4, &mbox_error); 1519 SMC_RET1(handle, status); 1520 } 1521 1522 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1523 { 1524 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1525 GET_JOB_ID(x1), 1526 MBOX_CMD_GET_CHIPID, 1527 NULL, 1528 0U, 1529 MBOX_CMD_FLAG_CASUAL, 1530 sip_smc_get_chipid_cb, 1531 NULL, 1532 0); 1533 SMC_RET1(handle, status); 1534 } 1535 1536 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1537 { 1538 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1539 (uint32_t *) &x4, &mbox_error); 1540 SMC_RET1(handle, status); 1541 } 1542 1543 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1544 { 1545 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1546 x2, &mbox_error); 1547 SMC_RET1(handle, status); 1548 } 1549 1550 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1551 { 1552 if (x4 == FCS_MODE_ENCRYPT) { 1553 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1554 x5, x6, x7, (uint32_t *) &x8, 1555 &mbox_error, x10, x11); 1556 } else if (x4 == FCS_MODE_DECRYPT) { 1557 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1558 x5, x6, x7, (uint32_t *) &x8, 1559 &mbox_error, x9, x10, x11); 1560 } else { 1561 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1562 status = INTEL_SIP_SMC_STATUS_REJECTED; 1563 } 1564 SMC_RET1(handle, status); 1565 } 1566 1567 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1568 { 1569 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1570 SMC_RET1(handle, status); 1571 } 1572 1573 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1574 { 1575 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1576 GET_JOB_ID(x1), 1577 MBOX_FCS_OPEN_CS_SESSION, 1578 NULL, 1579 0U, 1580 MBOX_CMD_FLAG_CASUAL, 1581 sip_smc_cmd_cb_ret3, 1582 NULL, 1583 0); 1584 SMC_RET1(handle, status); 1585 } 1586 1587 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1588 { 1589 uint32_t session_id = (uint32_t)x2; 1590 1591 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1592 GET_JOB_ID(x1), 1593 MBOX_FCS_CLOSE_CS_SESSION, 1594 &session_id, 1595 1U, 1596 MBOX_CMD_FLAG_CASUAL, 1597 sip_smc_cmd_cb_ret2, 1598 NULL, 1599 0); 1600 SMC_RET1(handle, status); 1601 } 1602 1603 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1604 { 1605 uint64_t key_addr = x2; 1606 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1607 1608 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1609 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1610 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1611 smc_fid); 1612 status = INTEL_SIP_SMC_STATUS_REJECTED; 1613 SMC_RET1(handle, status); 1614 } 1615 1616 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1617 GET_JOB_ID(x1), 1618 MBOX_FCS_IMPORT_CS_KEY, 1619 (uint32_t *)key_addr, 1620 key_len_words, 1621 MBOX_CMD_FLAG_CASUAL, 1622 sip_smc_cmd_cb_ret3, 1623 NULL, 1624 0); 1625 SMC_RET1(handle, status); 1626 } 1627 1628 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1629 { 1630 uint64_t key_addr = x2; 1631 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1632 1633 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1634 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1635 status = INTEL_SIP_SMC_STATUS_REJECTED; 1636 SMC_RET1(handle, status); 1637 } 1638 1639 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1640 GET_JOB_ID(x1), 1641 MBOX_FCS_CREATE_CS_KEY, 1642 (uint32_t *)key_addr, 1643 key_len_words, 1644 MBOX_CMD_FLAG_CASUAL, 1645 sip_smc_cmd_cb_ret3, 1646 NULL, 1647 0); 1648 SMC_RET1(handle, status); 1649 } 1650 1651 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1652 { 1653 uint32_t session_id = (uint32_t)x2; 1654 uint32_t key_uid = (uint32_t)x3; 1655 uint64_t ret_key_addr = (uint64_t)x4; 1656 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1657 1658 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1659 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1660 status = INTEL_SIP_SMC_STATUS_REJECTED; 1661 SMC_RET1(handle, status); 1662 } 1663 1664 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1665 RESERVED_AS_ZERO, key_uid}; 1666 1667 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1668 GET_JOB_ID(x1), 1669 MBOX_FCS_EXPORT_CS_KEY, 1670 (uint32_t *)&payload, 1671 sizeof(payload) / MBOX_WORD_BYTE, 1672 MBOX_CMD_FLAG_CASUAL, 1673 sip_smc_ret_nbytes_cb, 1674 (uint32_t *)ret_key_addr, 1675 2); 1676 SMC_RET1(handle, status); 1677 } 1678 1679 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1680 { 1681 uint32_t session_id = (uint32_t)x2; 1682 uint32_t key_uid = (uint32_t)x3; 1683 1684 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1685 RESERVED_AS_ZERO, key_uid}; 1686 1687 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1688 GET_JOB_ID(x1), 1689 MBOX_FCS_REMOVE_CS_KEY, 1690 (uint32_t *)&payload, 1691 sizeof(payload) / MBOX_WORD_BYTE, 1692 MBOX_CMD_FLAG_CASUAL, 1693 sip_smc_cmd_cb_ret3, 1694 NULL, 1695 0); 1696 SMC_RET1(handle, status); 1697 } 1698 1699 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1700 { 1701 uint32_t session_id = (uint32_t)x2; 1702 uint32_t key_uid = (uint32_t)x3; 1703 uint64_t ret_key_addr = (uint64_t)x4; 1704 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1705 1706 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1707 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1708 status = INTEL_SIP_SMC_STATUS_REJECTED; 1709 SMC_RET1(handle, status); 1710 } 1711 1712 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1713 RESERVED_AS_ZERO, key_uid}; 1714 1715 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1716 GET_JOB_ID(x1), 1717 MBOX_FCS_GET_CS_KEY_INFO, 1718 (uint32_t *)&payload, 1719 sizeof(payload) / MBOX_WORD_BYTE, 1720 MBOX_CMD_FLAG_CASUAL, 1721 sip_smc_ret_nbytes_cb, 1722 (uint32_t *)ret_key_addr, 1723 2); 1724 SMC_RET1(handle, status); 1725 } 1726 1727 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1728 { 1729 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1730 x6, &mbox_error); 1731 SMC_RET1(handle, status); 1732 } 1733 1734 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1735 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1736 { 1737 uint32_t job_id = 0U; 1738 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1739 true : false; 1740 1741 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1742 x3, x4, x5, x6, x7, x8, is_final, 1743 &job_id, x9, x10); 1744 SMC_RET1(handle, status); 1745 } 1746 1747 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1748 { 1749 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1750 &mbox_error); 1751 SMC_RET1(handle, status); 1752 } 1753 1754 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1755 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1756 { 1757 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1758 true : false; 1759 1760 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1761 x3, x4, x5, x6, (uint32_t *) &x7, 1762 is_final, &mbox_error, x8); 1763 1764 SMC_RET1(handle, status); 1765 } 1766 1767 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1768 { 1769 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1770 &mbox_error); 1771 SMC_RET1(handle, status); 1772 } 1773 1774 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1775 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1776 { 1777 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1778 true : false; 1779 1780 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1781 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1782 is_final, &mbox_error, x9); 1783 SMC_RET1(handle, status); 1784 } 1785 1786 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1787 { 1788 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1789 &mbox_error); 1790 SMC_RET1(handle, status); 1791 } 1792 1793 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1794 { 1795 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1796 x4, x5, x6, (uint32_t *) &x7, 1797 &mbox_error); 1798 SMC_RET1(handle, status); 1799 } 1800 1801 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1802 { 1803 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1804 &mbox_error); 1805 SMC_RET1(handle, status); 1806 } 1807 1808 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1809 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1810 { 1811 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1812 ? true : false; 1813 1814 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1815 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1816 is_final, &mbox_error, x8); 1817 SMC_RET1(handle, status); 1818 } 1819 1820 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1821 { 1822 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1823 x6, &mbox_error); 1824 SMC_RET1(handle, status); 1825 } 1826 1827 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1828 { 1829 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1830 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1831 &mbox_error); 1832 SMC_RET1(handle, status); 1833 } 1834 1835 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1836 { 1837 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1838 x5, x6, &mbox_error); 1839 SMC_RET1(handle, status); 1840 } 1841 1842 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1843 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1844 { 1845 bool is_final = (smc_fid == 1846 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1847 true : false; 1848 1849 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1850 smc_fid, x1, x2, x3, x4, x5, x6, 1851 (uint32_t *) &x7, x8, is_final, 1852 &mbox_error, x9); 1853 SMC_RET1(handle, status); 1854 } 1855 1856 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1857 { 1858 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1859 &mbox_error); 1860 SMC_RET1(handle, status); 1861 } 1862 1863 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1864 { 1865 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1866 x4, (uint32_t *) &x5, &mbox_error); 1867 SMC_RET1(handle, status); 1868 } 1869 1870 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1871 { 1872 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1873 &mbox_error); 1874 SMC_RET1(handle, status); 1875 } 1876 1877 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1878 { 1879 uint32_t dest_size = (uint32_t)x7; 1880 1881 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1882 __func__, __LINE__, (uint32_t)x7, dest_size); 1883 1884 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1885 x4, x5, x6, (uint32_t *) &dest_size, 1886 &mbox_error); 1887 SMC_RET1(handle, status); 1888 } 1889 1890 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1891 { 1892 uint32_t *src_addr = (uint32_t *)x2; 1893 uint32_t src_size = (uint32_t)x3; 1894 uint32_t *dst_addr = (uint32_t *)x4; 1895 1896 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1897 GET_JOB_ID(x1), 1898 MBOX_CMD_MCTP_MSG, 1899 src_addr, 1900 src_size / MBOX_WORD_BYTE, 1901 MBOX_CMD_FLAG_CASUAL, 1902 sip_smc_ret_nbytes_cb, 1903 dst_addr, 1904 2); 1905 1906 SMC_RET1(handle, status); 1907 } 1908 1909 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1910 { 1911 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1912 x7); 1913 SMC_RET1(handle, status); 1914 } 1915 1916 default: 1917 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1918 cookie, handle, flags); 1919 } /* switch (smc_fid) */ 1920 } 1921 #endif 1922 1923 /* 1924 * This function is responsible for handling all SiP calls from the NS world 1925 */ 1926 1927 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1928 u_register_t x1, 1929 u_register_t x2, 1930 u_register_t x3, 1931 u_register_t x4, 1932 void *cookie, 1933 void *handle, 1934 u_register_t flags) 1935 { 1936 uint32_t retval = 0, completed_addr[3]; 1937 uint32_t retval2 = 0; 1938 uint32_t mbox_error = 0; 1939 uint32_t err_states = 0; 1940 uint64_t retval64, rsu_respbuf[9]; 1941 uint32_t seu_respbuf[3]; 1942 int status = INTEL_SIP_SMC_STATUS_OK; 1943 int mbox_status; 1944 unsigned int len_in_resp = 0; 1945 u_register_t x5, x6, x7; 1946 1947 switch (smc_fid) { 1948 case SIP_SVC_UID: 1949 /* Return UID to the caller */ 1950 SMC_UUID_RET(handle, intl_svc_uid); 1951 1952 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1953 status = intel_mailbox_fpga_config_isdone(&err_states); 1954 SMC_RET4(handle, status, err_states, 0, 0); 1955 1956 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1957 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1958 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1959 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1960 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1961 1962 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1963 status = intel_fpga_config_start(x1); 1964 SMC_RET4(handle, status, 0, 0, 0); 1965 1966 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1967 status = intel_fpga_config_write(x1, x2); 1968 SMC_RET4(handle, status, 0, 0, 0); 1969 1970 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1971 status = intel_fpga_config_completed_write(completed_addr, 1972 &retval, &rcv_id); 1973 switch (retval) { 1974 case 1: 1975 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1976 completed_addr[0], 0, 0); 1977 1978 case 2: 1979 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1980 completed_addr[0], 1981 completed_addr[1], 0); 1982 1983 case 3: 1984 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1985 completed_addr[0], 1986 completed_addr[1], 1987 completed_addr[2]); 1988 1989 case 0: 1990 SMC_RET4(handle, status, 0, 0, 0); 1991 1992 default: 1993 mailbox_clear_response(); 1994 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1995 } 1996 1997 case INTEL_SIP_SMC_REG_READ: 1998 status = intel_secure_reg_read(x1, &retval); 1999 SMC_RET3(handle, status, retval, x1); 2000 2001 case INTEL_SIP_SMC_REG_WRITE: 2002 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 2003 SMC_RET3(handle, status, retval, x1); 2004 2005 case INTEL_SIP_SMC_REG_UPDATE: 2006 status = intel_secure_reg_update(x1, (uint32_t)x2, 2007 (uint32_t)x3, &retval); 2008 SMC_RET3(handle, status, retval, x1); 2009 2010 case INTEL_SIP_SMC_RSU_STATUS: 2011 status = intel_rsu_status(rsu_respbuf, 2012 ARRAY_SIZE(rsu_respbuf)); 2013 if (status) { 2014 SMC_RET1(handle, status); 2015 } else { 2016 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 2017 rsu_respbuf[2], rsu_respbuf[3]); 2018 } 2019 2020 case INTEL_SIP_SMC_RSU_UPDATE: 2021 status = intel_rsu_update(x1); 2022 SMC_RET1(handle, status); 2023 2024 case INTEL_SIP_SMC_RSU_NOTIFY: 2025 status = intel_rsu_notify(x1); 2026 SMC_RET1(handle, status); 2027 2028 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 2029 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 2030 ARRAY_SIZE(rsu_respbuf), &retval); 2031 if (status) { 2032 SMC_RET1(handle, status); 2033 } else { 2034 SMC_RET2(handle, status, retval); 2035 } 2036 2037 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 2038 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2039 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 2040 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 2041 2042 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 2043 status = intel_rsu_copy_dcmf_version(x1, x2); 2044 SMC_RET1(handle, status); 2045 2046 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 2047 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 2048 ARRAY_SIZE(rsu_respbuf)); 2049 if (status) { 2050 SMC_RET1(handle, status); 2051 } else { 2052 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 2053 rsu_respbuf[2], rsu_respbuf[3]); 2054 } 2055 2056 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 2057 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 2058 ((uint64_t)rsu_dcmf_stat[3] << 48) | 2059 ((uint64_t)rsu_dcmf_stat[2] << 32) | 2060 ((uint64_t)rsu_dcmf_stat[1] << 16) | 2061 rsu_dcmf_stat[0]); 2062 2063 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 2064 status = intel_rsu_copy_dcmf_status(x1); 2065 SMC_RET1(handle, status); 2066 2067 case INTEL_SIP_SMC_RSU_MAX_RETRY: 2068 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 2069 2070 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 2071 rsu_max_retry = x1; 2072 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2073 2074 case INTEL_SIP_SMC_ECC_DBE: 2075 status = intel_ecc_dbe_notification(x1); 2076 SMC_RET1(handle, status); 2077 2078 case INTEL_SIP_SMC_SERVICE_COMPLETED: 2079 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 2080 &len_in_resp, &mbox_error); 2081 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 2082 2083 case INTEL_SIP_SMC_FIRMWARE_VERSION: 2084 status = intel_smc_fw_version(&retval); 2085 SMC_RET2(handle, status, retval); 2086 2087 case INTEL_SIP_SMC_MBOX_SEND_CMD: 2088 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2089 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2090 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 2091 &mbox_status, &len_in_resp); 2092 SMC_RET3(handle, status, mbox_status, len_in_resp); 2093 2094 case INTEL_SIP_SMC_GET_USERCODE: 2095 status = intel_smc_get_usercode(&retval); 2096 SMC_RET2(handle, status, retval); 2097 2098 case INTEL_SIP_SMC_FCS_CRYPTION: 2099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2100 2101 if (x1 == FCS_MODE_DECRYPT) { 2102 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 2103 } else if (x1 == FCS_MODE_ENCRYPT) { 2104 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 2105 } else { 2106 status = INTEL_SIP_SMC_STATUS_REJECTED; 2107 } 2108 2109 SMC_RET3(handle, status, x4, x5); 2110 2111 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 2112 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2113 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2114 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2115 2116 if (x3 == FCS_MODE_DECRYPT) { 2117 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2118 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 2119 } else if (x3 == FCS_MODE_ENCRYPT) { 2120 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2121 (uint32_t *) &x7, &mbox_error, 0, 0); 2122 } else { 2123 status = INTEL_SIP_SMC_STATUS_REJECTED; 2124 } 2125 2126 SMC_RET4(handle, status, mbox_error, x6, x7); 2127 2128 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2129 status = intel_fcs_random_number_gen(x1, &retval64, 2130 &mbox_error); 2131 SMC_RET4(handle, status, mbox_error, x1, retval64); 2132 2133 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2134 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2135 &send_id); 2136 SMC_RET1(handle, status); 2137 2138 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2139 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2140 SMC_RET1(handle, status); 2141 2142 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2143 status = intel_fcs_get_provision_data(&send_id); 2144 SMC_RET1(handle, status); 2145 2146 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2147 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2148 &mbox_error); 2149 SMC_RET2(handle, status, mbox_error); 2150 2151 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2152 status = intel_hps_set_bridges(x1, x2); 2153 SMC_RET1(handle, status); 2154 2155 case INTEL_SIP_SMC_HWMON_READTEMP: 2156 status = intel_hwmon_readtemp(x1, &retval); 2157 SMC_RET2(handle, status, retval); 2158 2159 case INTEL_SIP_SMC_HWMON_READVOLT: 2160 status = intel_hwmon_readvolt(x1, &retval); 2161 SMC_RET2(handle, status, retval); 2162 2163 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2164 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2165 SMC_RET2(handle, status, mbox_error); 2166 2167 case INTEL_SIP_SMC_FCS_CHIP_ID: 2168 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2169 SMC_RET4(handle, status, mbox_error, retval, retval2); 2170 2171 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2172 status = intel_fcs_attestation_subkey(x1, x2, x3, 2173 (uint32_t *) &x4, &mbox_error); 2174 SMC_RET4(handle, status, mbox_error, x3, x4); 2175 2176 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2177 status = intel_fcs_get_measurement(x1, x2, x3, 2178 (uint32_t *) &x4, &mbox_error); 2179 SMC_RET4(handle, status, mbox_error, x3, x4); 2180 2181 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2182 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2183 (uint32_t *) &x3, &mbox_error); 2184 SMC_RET4(handle, status, mbox_error, x2, x3); 2185 2186 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2187 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2188 SMC_RET2(handle, status, mbox_error); 2189 2190 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2191 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2192 SMC_RET3(handle, status, mbox_error, retval); 2193 2194 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2195 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2196 SMC_RET2(handle, status, mbox_error); 2197 2198 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2199 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2200 SMC_RET1(handle, status); 2201 2202 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2203 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2204 (uint32_t *) &x4, &mbox_error); 2205 SMC_RET4(handle, status, mbox_error, x3, x4); 2206 2207 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2208 status = intel_fcs_remove_crypto_service_key(x1, x2, 2209 &mbox_error); 2210 SMC_RET2(handle, status, mbox_error); 2211 2212 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2213 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2214 (uint32_t *) &x4, &mbox_error); 2215 SMC_RET4(handle, status, mbox_error, x3, x4); 2216 2217 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2218 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2219 status = intel_fcs_get_digest_init(x1, x2, x3, 2220 x4, x5, &mbox_error); 2221 SMC_RET2(handle, status, mbox_error); 2222 2223 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2224 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2225 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2226 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2227 x3, x4, x5, (uint32_t *) &x6, false, 2228 &mbox_error, 0); 2229 SMC_RET4(handle, status, mbox_error, x5, x6); 2230 2231 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2232 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2233 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2234 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2235 x3, x4, x5, (uint32_t *) &x6, true, 2236 &mbox_error, 0); 2237 SMC_RET4(handle, status, mbox_error, x5, x6); 2238 2239 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2240 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2241 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2242 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2243 x4, x5, (uint32_t *) &x6, false, 2244 &mbox_error, &send_id); 2245 SMC_RET4(handle, status, mbox_error, x5, x6); 2246 2247 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2248 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2249 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2250 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2251 x4, x5, (uint32_t *) &x6, true, 2252 &mbox_error, &send_id); 2253 SMC_RET4(handle, status, mbox_error, x5, x6); 2254 2255 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2256 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2257 status = intel_fcs_mac_verify_init(x1, x2, x3, 2258 x4, x5, &mbox_error); 2259 SMC_RET2(handle, status, mbox_error); 2260 2261 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2262 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2263 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2264 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2265 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2266 x3, x4, x5, (uint32_t *) &x6, x7, false, 2267 &mbox_error, 0); 2268 SMC_RET4(handle, status, mbox_error, x5, x6); 2269 2270 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2271 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2272 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2273 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2274 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2275 x3, x4, x5, (uint32_t *) &x6, x7, true, 2276 &mbox_error, 0); 2277 SMC_RET4(handle, status, mbox_error, x5, x6); 2278 2279 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2280 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2281 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2282 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2283 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2284 x4, x5, (uint32_t *) &x6, x7, 2285 false, &mbox_error, &send_id); 2286 SMC_RET4(handle, status, mbox_error, x5, x6); 2287 2288 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2289 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2290 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2291 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2292 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2293 x4, x5, (uint32_t *) &x6, x7, 2294 true, &mbox_error, &send_id); 2295 SMC_RET4(handle, status, mbox_error, x5, x6); 2296 2297 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2298 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2299 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2300 x4, x5, &mbox_error); 2301 SMC_RET2(handle, status, mbox_error); 2302 2303 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2304 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2305 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2306 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2307 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2308 false, &mbox_error, 0); 2309 SMC_RET4(handle, status, mbox_error, x5, x6); 2310 2311 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2312 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2313 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2314 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2315 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2316 true, &mbox_error, 0); 2317 SMC_RET4(handle, status, mbox_error, x5, x6); 2318 2319 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2320 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2321 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2322 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2323 x2, x3, x4, x5, (uint32_t *) &x6, false, 2324 &mbox_error, &send_id); 2325 SMC_RET4(handle, status, mbox_error, x5, x6); 2326 2327 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2328 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2329 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2330 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2331 x2, x3, x4, x5, (uint32_t *) &x6, true, 2332 &mbox_error, &send_id); 2333 SMC_RET4(handle, status, mbox_error, x5, x6); 2334 2335 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2336 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2337 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2338 x4, x5, &mbox_error); 2339 SMC_RET2(handle, status, mbox_error); 2340 2341 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2342 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2343 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2344 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2345 x3, x4, x5, (uint32_t *) &x6, 2346 &mbox_error); 2347 SMC_RET4(handle, status, mbox_error, x5, x6); 2348 2349 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2350 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2351 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2352 x4, x5, &mbox_error); 2353 SMC_RET2(handle, status, mbox_error); 2354 2355 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2356 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2357 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2358 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2359 x2, x3, x4, x5, (uint32_t *) &x6, 2360 &mbox_error); 2361 SMC_RET4(handle, status, mbox_error, x5, x6); 2362 2363 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2364 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2365 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2366 x4, x5, &mbox_error); 2367 SMC_RET2(handle, status, mbox_error); 2368 2369 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2370 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2371 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2372 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2373 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2374 smc_fid, 0, x1, x2, x3, x4, x5, 2375 (uint32_t *) &x6, x7, false, 2376 &mbox_error, 0); 2377 SMC_RET4(handle, status, mbox_error, x5, x6); 2378 2379 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2380 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2381 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2382 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2383 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2384 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2385 x7, false, &mbox_error, &send_id); 2386 SMC_RET4(handle, status, mbox_error, x5, x6); 2387 2388 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2389 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2390 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2391 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2392 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2393 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2394 x7, true, &mbox_error, &send_id); 2395 SMC_RET4(handle, status, mbox_error, x5, x6); 2396 2397 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2398 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2399 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2400 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2401 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2402 smc_fid, 0, x1, x2, x3, x4, x5, 2403 (uint32_t *) &x6, x7, true, 2404 &mbox_error, 0); 2405 SMC_RET4(handle, status, mbox_error, x5, x6); 2406 2407 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2408 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2409 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2410 x4, x5, &mbox_error); 2411 SMC_RET2(handle, status, mbox_error); 2412 2413 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2414 status = intel_fcs_ecdsa_get_pubkey_finalize( 2415 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2416 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2417 SMC_RET4(handle, status, mbox_error, x3, x4); 2418 2419 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2420 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2421 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2422 x4, x5, &mbox_error); 2423 SMC_RET2(handle, status, mbox_error); 2424 2425 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2426 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2427 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2428 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2429 x4, x5, (uint32_t *) &x6, &mbox_error); 2430 SMC_RET4(handle, status, mbox_error, x5, x6); 2431 2432 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2433 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2434 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2435 &mbox_error); 2436 SMC_RET2(handle, status, mbox_error); 2437 2438 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2439 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2440 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2441 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2442 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2443 SMC_RET1(handle, status); 2444 2445 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2446 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2447 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2448 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2449 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2450 SMC_RET1(handle, status); 2451 2452 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2453 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2454 status = intel_smmu_hps_remapper_config(x1); 2455 SMC_RET1(handle, status); 2456 #endif 2457 2458 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2459 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2460 &mbox_error); 2461 SMC_RET4(handle, status, mbox_error, x1, retval64); 2462 2463 case INTEL_SIP_SMC_SVC_VERSION: 2464 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2465 SIP_SVC_VERSION_MAJOR, 2466 SIP_SVC_VERSION_MINOR); 2467 2468 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2469 status = intel_sdm_seu_err_read(seu_respbuf, 2470 ARRAY_SIZE(seu_respbuf)); 2471 if (status) { 2472 SMC_RET1(handle, status); 2473 } else { 2474 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2475 } 2476 2477 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2478 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2479 SMC_RET1(handle, status); 2480 2481 case INTEL_SIP_SMC_ATF_BUILD_VER: 2482 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2483 VERSION_MINOR, VERSION_PATCH); 2484 2485 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2486 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2487 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2488 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2489 #endif 2490 2491 default: 2492 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2493 cookie, handle, flags); 2494 } 2495 } 2496 2497 uintptr_t sip_smc_handler(uint32_t smc_fid, 2498 u_register_t x1, 2499 u_register_t x2, 2500 u_register_t x3, 2501 u_register_t x4, 2502 void *cookie, 2503 void *handle, 2504 u_register_t flags) 2505 { 2506 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2507 2508 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2509 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2510 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2511 cookie, handle, flags); 2512 } 2513 #if SIP_SVC_V3 2514 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2515 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2516 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2517 cookie, handle, flags); 2518 return ret; 2519 } 2520 #endif 2521 else { 2522 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2523 cookie, handle, flags); 2524 } 2525 } 2526 2527 DECLARE_RT_SVC( 2528 socfpga_sip_svc, 2529 OEN_SIP_START, 2530 OEN_SIP_END, 2531 SMC_TYPE_FAST, 2532 NULL, 2533 sip_smc_handler 2534 ); 2535 2536 DECLARE_RT_SVC( 2537 socfpga_sip_svc_std, 2538 OEN_SIP_START, 2539 OEN_SIP_END, 2540 SMC_TYPE_YIELD, 2541 NULL, 2542 sip_smc_handler 2543 ); 2544