1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/board/common/rotpk/rotpk_def.h> 16 #include <plat/arm/common/smccc_def.h> 17 #include <plat/common/common_def.h> 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 /* Special value used to verify platform parameters from BL2 to BL31 */ 24 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 25 26 #define ARM_SYSTEM_COUNT U(1) 27 28 #define ARM_CACHE_WRITEBACK_SHIFT 6 29 30 /* 31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 32 * power levels have a 1:1 mapping with the MPIDR affinity levels. 33 */ 34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 35 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 36 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 37 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 38 39 /* 40 * Macros for local power states in ARM platforms encoded by State-ID field 41 * within the power-state parameter. 42 */ 43 /* Local power state for power domains in Run state. */ 44 #define ARM_LOCAL_STATE_RUN U(0) 45 /* Local power state for retention. Valid only for CPU power domains */ 46 #define ARM_LOCAL_STATE_RET U(1) 47 /* Local power state for OFF/power-down. Valid for CPU and cluster power 48 domains */ 49 #define ARM_LOCAL_STATE_OFF U(2) 50 51 /* Memory location options for TSP */ 52 #define ARM_TRUSTED_SRAM_ID 0 53 #define ARM_TRUSTED_DRAM_ID 1 54 #define ARM_DRAM_ID 2 55 56 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 57 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 58 #else 59 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 60 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 61 62 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 63 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 64 65 /* The remaining Trusted SRAM is used to load the BL images */ 66 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 67 ARM_SHARED_RAM_SIZE) 68 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 69 ARM_SHARED_RAM_SIZE) 70 71 /* 72 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 73 * follows: 74 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 75 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 76 * - REALM DRAM: Reserved for Realm world if RME is enabled 77 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 78 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 79 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 80 * 81 * RME enabled(64MB) RME not enabled(16MB) 82 * -------------------- ------------------- 83 * | | | | 84 * | AP TZC (~28MB) | | AP TZC (~14MB) | 85 * -------------------- ------------------- 86 * | Event Log | | Event Log | 87 * | (4KB) | | (4KB) | 88 * -------------------- ------------------- 89 * | REALM (RMM) | | | 90 * | (32MB - 4KB) | | EL3 TZC (2MB) | 91 * -------------------- ------------------- 92 * | | | | 93 * | TF-A <-> RMM | | SCP TZC | 94 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 95 * -------------------- 96 * | | 97 * | EL3 TZC (3MB) | 98 * -------------------- 99 * | L1 GPT + SCP TZC | 100 * | (~1MB) | 101 * 0xFFFF_FFFF -------------------- 102 */ 103 #if ENABLE_RME 104 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 105 /* 106 * Define a region within the TZC secured DRAM for use by EL3 runtime 107 * firmware. This region is meant to be NOLOAD and will not be zero 108 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 109 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 110 */ 111 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 112 /* 8 x 128KB L1 pages (GPCCR_PPS_64GB, GPCCR_PGS_4K) */ 113 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 114 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 115 #define ARM_REALM_SIZE (UL(0x02000000) - \ 116 ARM_EL3_RMM_SHARED_SIZE) 117 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 118 #else 119 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 120 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 121 #define ARM_L1_GPT_SIZE UL(0) 122 #define ARM_REALM_SIZE UL(0) 123 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 124 #endif /* ENABLE_RME */ 125 126 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 127 ARM_DRAM1_SIZE - \ 128 (ARM_SCP_TZC_DRAM1_SIZE + \ 129 ARM_L1_GPT_SIZE)) 130 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 131 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 132 ARM_SCP_TZC_DRAM1_SIZE - 1U) 133 134 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 135 MEASURED_BOOT 136 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 137 138 #if ENABLE_RME 139 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 140 ARM_EVENT_LOG_DRAM1_SIZE) 141 #else 142 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 143 ARM_EVENT_LOG_DRAM1_SIZE) 144 #endif /* ENABLE_RME */ 145 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 146 ARM_EVENT_LOG_DRAM1_SIZE - \ 147 1U) 148 #else 149 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 150 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 151 152 #if ENABLE_RME 153 #define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \ 154 ARM_DRAM1_SIZE - \ 155 ARM_L1_GPT_SIZE) 156 #define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \ 157 ARM_L1_GPT_SIZE - 1U) 158 159 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 160 ARM_REALM_SIZE) 161 162 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 163 164 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 165 ARM_DRAM1_SIZE - \ 166 (ARM_SCP_TZC_DRAM1_SIZE + \ 167 ARM_L1_GPT_SIZE + \ 168 ARM_EL3_RMM_SHARED_SIZE + \ 169 ARM_EL3_TZC_DRAM1_SIZE)) 170 171 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 172 ARM_EL3_RMM_SHARED_SIZE - 1U) 173 #endif /* ENABLE_RME */ 174 175 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 176 ARM_EL3_TZC_DRAM1_SIZE) 177 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 178 ARM_EL3_TZC_DRAM1_SIZE - 1U) 179 180 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 181 ARM_DRAM1_SIZE - \ 182 ARM_TZC_DRAM1_SIZE) 183 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 184 (ARM_SCP_TZC_DRAM1_SIZE + \ 185 ARM_EL3_TZC_DRAM1_SIZE + \ 186 ARM_EL3_RMM_SHARED_SIZE + \ 187 ARM_REALM_SIZE + \ 188 ARM_L1_GPT_SIZE + \ 189 ARM_EVENT_LOG_DRAM1_SIZE)) 190 191 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 192 ARM_AP_TZC_DRAM1_SIZE - 1U) 193 194 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 195 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 196 197 #ifdef SPD_opteed 198 /* 199 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 200 * load/authenticate the trusted os extra image. The first 512KB of 201 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 202 * for OPTEE is paged image which only include the paging part using 203 * virtual memory but without "init" data. OPTEE will copy the "init" data 204 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 205 * extra image behind the "init" data. 206 */ 207 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 208 ARM_AP_TZC_DRAM1_SIZE - \ 209 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 210 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 211 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 212 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 213 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 214 MT_MEMORY | MT_RW | MT_SECURE) 215 216 /* 217 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 218 * support is enabled). 219 */ 220 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 221 BL32_BASE, \ 222 BL32_LIMIT - BL32_BASE, \ 223 MT_MEMORY | MT_RW | MT_SECURE) 224 #endif /* SPD_opteed */ 225 226 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 227 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 228 ARM_TZC_DRAM1_SIZE) 229 230 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 231 ARM_NS_DRAM1_SIZE - 1U) 232 #ifdef PLAT_ARM_DRAM1_BASE 233 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 234 #else 235 #define ARM_DRAM1_BASE ULL(0x80000000) 236 #endif /* PLAT_ARM_DRAM1_BASE */ 237 238 #define ARM_DRAM1_SIZE ULL(0x80000000) 239 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 240 ARM_DRAM1_SIZE - 1U) 241 242 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 243 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 244 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 245 ARM_DRAM2_SIZE - 1U) 246 /* Number of DRAM banks */ 247 #define ARM_DRAM_NUM_BANKS 2UL 248 249 /* Number of PCIe memory regions */ 250 #define ARM_PCI_NUM_REGIONS 2UL 251 252 #define ARM_IRQ_SEC_PHY_TIMER 29 253 254 #define ARM_IRQ_SEC_SGI_0 8 255 #define ARM_IRQ_SEC_SGI_1 9 256 #define ARM_IRQ_SEC_SGI_2 10 257 #define ARM_IRQ_SEC_SGI_3 11 258 #define ARM_IRQ_SEC_SGI_4 12 259 #define ARM_IRQ_SEC_SGI_5 13 260 #define ARM_IRQ_SEC_SGI_6 14 261 #define ARM_IRQ_SEC_SGI_7 15 262 263 /* 264 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 265 * terminology. On a GICv2 system or mode, the lists will be merged and treated 266 * as Group 0 interrupts. 267 */ 268 #define ARM_G1S_IRQ_PROPS(grp) \ 269 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 270 GIC_INTR_CFG_LEVEL), \ 271 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 272 GIC_INTR_CFG_EDGE), \ 273 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 274 GIC_INTR_CFG_EDGE), \ 275 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 276 GIC_INTR_CFG_EDGE), \ 277 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 278 GIC_INTR_CFG_EDGE), \ 279 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 280 GIC_INTR_CFG_EDGE), \ 281 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 282 GIC_INTR_CFG_EDGE) 283 284 #define ARM_G0_IRQ_PROPS(grp) \ 285 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 286 GIC_INTR_CFG_EDGE), \ 287 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 288 GIC_INTR_CFG_EDGE) 289 290 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 291 ARM_SHARED_RAM_BASE, \ 292 ARM_SHARED_RAM_SIZE, \ 293 MT_DEVICE | MT_RW | EL3_PAS) 294 295 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 296 ARM_NS_DRAM1_BASE, \ 297 ARM_NS_DRAM1_SIZE, \ 298 MT_MEMORY | MT_RW | MT_NS) 299 300 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 301 ARM_DRAM2_BASE, \ 302 ARM_DRAM2_SIZE, \ 303 MT_MEMORY | MT_RW | MT_NS) 304 305 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 306 TSP_SEC_MEM_BASE, \ 307 TSP_SEC_MEM_SIZE, \ 308 MT_MEMORY | MT_RW | MT_SECURE) 309 310 #if ARM_BL31_IN_DRAM 311 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 312 BL31_BASE, \ 313 PLAT_ARM_MAX_BL31_SIZE, \ 314 MT_MEMORY | MT_RW | MT_SECURE) 315 #endif 316 317 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 318 ARM_EL3_TZC_DRAM1_BASE, \ 319 ARM_EL3_TZC_DRAM1_SIZE, \ 320 MT_MEMORY | MT_RW | EL3_PAS) 321 322 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 323 PLAT_ARM_TRUSTED_DRAM_BASE, \ 324 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 325 MT_MEMORY | MT_RW | MT_SECURE) 326 327 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 328 MEASURED_BOOT 329 #define ARM_MAP_EVENT_LOG_DRAM1 \ 330 MAP_REGION_FLAT( \ 331 ARM_EVENT_LOG_DRAM1_BASE, \ 332 ARM_EVENT_LOG_DRAM1_SIZE, \ 333 MT_MEMORY | MT_RW | MT_SECURE) 334 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 335 336 #if ENABLE_RME 337 /* 338 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 339 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 340 */ 341 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 342 PLAT_ARM_RMM_BASE, \ 343 (PLAT_ARM_RMM_SIZE + \ 344 ARM_EL3_RMM_SHARED_SIZE), \ 345 MT_MEMORY | MT_RW | MT_REALM) 346 347 348 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 349 ARM_L1_GPT_BASE, \ 350 ARM_L1_GPT_SIZE, \ 351 MT_MEMORY | MT_RW | EL3_PAS) 352 353 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 354 MAP_REGION_FLAT( \ 355 ARM_EL3_RMM_SHARED_BASE, \ 356 ARM_EL3_RMM_SHARED_SIZE, \ 357 MT_MEMORY | MT_RW | MT_REALM) 358 359 #endif /* ENABLE_RME */ 360 361 /* 362 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 363 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 364 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 365 * to be able to access the heap. 366 */ 367 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 368 BL1_RW_BASE, \ 369 BL1_RW_LIMIT - BL1_RW_BASE, \ 370 MT_MEMORY | MT_RW | EL3_PAS) 371 372 /* 373 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 374 * otherwise one region is defined containing both. 375 */ 376 #if SEPARATE_CODE_AND_RODATA 377 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 378 BL_CODE_BASE, \ 379 BL_CODE_END - BL_CODE_BASE, \ 380 MT_CODE | EL3_PAS), \ 381 MAP_REGION_FLAT( \ 382 BL_RO_DATA_BASE, \ 383 BL_RO_DATA_END \ 384 - BL_RO_DATA_BASE, \ 385 MT_RO_DATA | EL3_PAS) 386 #else 387 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 388 BL_CODE_BASE, \ 389 BL_CODE_END - BL_CODE_BASE, \ 390 MT_CODE | EL3_PAS) 391 #endif 392 #if USE_COHERENT_MEM 393 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 394 BL_COHERENT_RAM_BASE, \ 395 BL_COHERENT_RAM_END \ 396 - BL_COHERENT_RAM_BASE, \ 397 MT_DEVICE | MT_RW | EL3_PAS) 398 #endif 399 #if USE_ROMLIB 400 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 401 ROMLIB_RO_BASE, \ 402 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 403 MT_CODE | EL3_PAS) 404 405 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 406 ROMLIB_RW_BASE, \ 407 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 408 MT_MEMORY | MT_RW | EL3_PAS) 409 #endif 410 411 /* 412 * Map mem_protect flash region with read and write permissions 413 */ 414 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 415 V2M_FLASH_BLOCK_SIZE, \ 416 MT_DEVICE | MT_RW | MT_SECURE) 417 418 #if !TRANSFER_LIST 419 /* 420 * Map the region for device tree configuration with read and write permissions 421 */ 422 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 423 (ARM_FW_CONFIGS_LIMIT \ 424 - ARM_BL_RAM_BASE), \ 425 MT_MEMORY | MT_RW | EL3_PAS) 426 #endif 427 428 /* 429 * Map L0_GPT with read and write permissions 430 */ 431 #if ENABLE_RME 432 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_BASE, \ 433 ARM_L0_GPT_SIZE, \ 434 MT_MEMORY | MT_RW | MT_ROOT) 435 #endif 436 437 /* 438 * The max number of regions like RO(code), coherent and data required by 439 * different BL stages which need to be mapped in the MMU. 440 */ 441 #define ARM_BL_REGIONS 7 442 443 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 444 ARM_BL_REGIONS) 445 446 /* Memory mapped Generic timer interfaces */ 447 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 448 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 449 #else 450 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 451 #endif 452 453 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 454 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 455 #else 456 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 457 #endif 458 459 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 460 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 461 #else 462 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 463 #endif 464 465 #ifdef PLAT_ARM_SYS_CNT_BASE_S 466 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 467 #else 468 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 469 #endif 470 471 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 472 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 473 #else 474 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 475 #endif 476 477 #define ARM_CONSOLE_BAUDRATE 115200 478 479 /* Trusted Watchdog constants */ 480 #ifdef PLAT_ARM_SP805_TWDG_BASE 481 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 482 #else 483 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 484 #endif 485 #define ARM_SP805_TWDG_CLK_HZ 32768 486 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 487 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 488 #define ARM_TWDG_TIMEOUT_SEC 128 489 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 490 ARM_TWDG_TIMEOUT_SEC) 491 492 /****************************************************************************** 493 * Required platform porting definitions common to all ARM standard platforms 494 *****************************************************************************/ 495 496 /* 497 * This macro defines the deepest retention state possible. A higher state 498 * id will represent an invalid or a power down state. 499 */ 500 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 501 502 /* 503 * This macro defines the deepest power down states possible. Any state ID 504 * higher than this is invalid. 505 */ 506 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 507 508 /* 509 * Some data must be aligned on the biggest cache line size in the platform. 510 * This is known only to the platform as it might have a combination of 511 * integrated and external caches. 512 */ 513 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 514 515 /* Define memory configuration for trusted boot device tree files. */ 516 #ifdef PLAT_ARM_TB_FW_CONFIG_SIZE 517 #define ARM_TB_FW_CONFIG_MAX_SIZE PLAT_ARM_TB_FW_CONFIG_SIZE 518 #else 519 #define ARM_TB_FW_CONFIG_MAX_SIZE U(0x400) 520 #endif 521 522 #if !TRANSFER_LIST 523 /* 524 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 525 * and limit. Leave enough space of BL2 meminfo. 526 */ 527 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 528 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 529 + (PAGE_SIZE / 2U)) 530 531 /* 532 * Boot parameters passed from BL2 to BL31/BL32 are stored here 533 */ 534 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 535 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 536 + (PAGE_SIZE / 2U)) 537 538 /* 539 * Define limit of firmware configuration memory: 540 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 541 */ 542 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 543 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 544 #endif 545 546 #if ENABLE_RME 547 /* 548 * Store the L0 GPT on Trusted SRAM next to firmware 549 * configuration memory, 4KB aligned. 550 */ 551 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 552 #define ARM_L0_GPT_BASE (ARM_FW_CONFIGS_LIMIT) 553 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE) 554 #else 555 #define ARM_L0_GPT_SIZE U(0) 556 #endif 557 558 /******************************************************************************* 559 * BL1 specific defines. 560 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 561 * addresses. 562 ******************************************************************************/ 563 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 564 #ifdef PLAT_BL1_RO_LIMIT 565 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 566 #else 567 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 568 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 569 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 570 #endif 571 572 /* 573 * Put BL1 RW at the top of the Trusted SRAM. 574 */ 575 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 576 ARM_BL_RAM_SIZE - \ 577 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 578 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 579 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 580 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 581 582 #define ROMLIB_RO_BASE BL1_RO_LIMIT 583 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 584 585 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 586 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 587 588 /******************************************************************************* 589 * BL2 specific defines. 590 ******************************************************************************/ 591 #if RESET_TO_BL2 592 #if ENABLE_PIE 593 /* 594 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 595 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 596 */ 597 #define BL2_OFFSET (0x5000) 598 #else 599 /* Put BL2 towards the middle of the Trusted SRAM */ 600 #define BL2_OFFSET (0x2000) 601 #endif /* ENABLE_PIE */ 602 603 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 604 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 605 BL2_OFFSET) 606 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 607 608 #else 609 /* 610 * Put BL2 just below BL1. 611 */ 612 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 613 #define BL2_LIMIT BL1_RW_BASE 614 #endif 615 616 /******************************************************************************* 617 * BL31 specific defines. 618 ******************************************************************************/ 619 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 620 /* 621 * Put BL31 at the bottom of TZC secured DRAM 622 */ 623 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 624 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 625 PLAT_ARM_MAX_BL31_SIZE) 626 /* 627 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 628 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 629 */ 630 #if SEPARATE_NOBITS_REGION 631 #define BL31_NOBITS_BASE BL2_BASE 632 #define BL31_NOBITS_LIMIT BL2_LIMIT 633 #endif /* SEPARATE_NOBITS_REGION */ 634 #elif (RESET_TO_BL31) 635 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 636 # if !ENABLE_PIE 637 # error "BL31 must be a PIE if RESET_TO_BL31=1." 638 #endif 639 /* 640 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 641 * used for building BL31 and not used for loading BL31. 642 */ 643 # define BL31_BASE 0x0 644 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 645 #else 646 /* Put BL31 below BL2 in the Trusted SRAM.*/ 647 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 648 - PLAT_ARM_MAX_BL31_SIZE) 649 #define BL31_PROGBITS_LIMIT BL2_BASE 650 /* 651 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 652 * This is because in the RESET_TO_BL2 configuration, 653 * BL2 is always resident. 654 */ 655 #if RESET_TO_BL2 656 #define BL31_LIMIT BL2_BASE 657 #else 658 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 659 #endif 660 #endif 661 662 /****************************************************************************** 663 * RMM specific defines 664 *****************************************************************************/ 665 #if ENABLE_RME 666 #define RMM_BASE (ARM_REALM_BASE) 667 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 668 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 669 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 670 #endif 671 672 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 673 /******************************************************************************* 674 * BL32 specific defines for EL3 runtime in AArch32 mode 675 ******************************************************************************/ 676 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 677 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 678 # if !ENABLE_PIE 679 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 680 #endif 681 /* 682 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 683 * used for building BL32 and not used for loading BL32. 684 */ 685 # define BL32_BASE 0x0 686 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 687 # else 688 /* Put BL32 below BL2 in the Trusted SRAM.*/ 689 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 690 - PLAT_ARM_MAX_BL32_SIZE) 691 # define BL32_PROGBITS_LIMIT BL2_BASE 692 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 693 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 694 695 #else 696 /******************************************************************************* 697 * BL32 specific defines for EL3 runtime in AArch64 mode 698 ******************************************************************************/ 699 /* 700 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 701 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 702 * controller. 703 */ 704 # if SPM_MM || SPMC_AT_EL3 705 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 706 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 707 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 708 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 709 ARM_AP_TZC_DRAM1_SIZE) 710 # elif defined(SPD_spmd) 711 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 712 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 713 # define BL32_BASE PLAT_ARM_SPMC_BASE 714 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 715 PLAT_ARM_SPMC_SIZE) 716 # elif ARM_BL31_IN_DRAM 717 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 718 PLAT_ARM_MAX_BL31_SIZE) 719 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 720 PLAT_ARM_MAX_BL31_SIZE) 721 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 722 PLAT_ARM_MAX_BL31_SIZE) 723 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 724 ARM_AP_TZC_DRAM1_SIZE) 725 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 726 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 727 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 728 # define TSP_PROGBITS_LIMIT BL31_BASE 729 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 730 # define BL32_LIMIT BL31_BASE 731 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 732 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 733 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 734 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 735 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 736 + SZ_4M) 737 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 738 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 739 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 740 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 741 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 742 ARM_AP_TZC_DRAM1_SIZE) 743 # else 744 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 745 # endif 746 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 747 748 /* 749 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 750 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 751 * used as BL32. 752 */ 753 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 754 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 755 # undef BL32_BASE 756 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 757 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 758 759 #if RESET_TO_BL31 && defined(SPD_spmd) && defined(PLAT_ARM_SPMC_MANIFEST_BASE) 760 #define ARM_SPMC_MANIFEST_BASE PLAT_ARM_SPMC_MANIFEST_BASE 761 #else 762 763 /* 764 * SPM expects SPM Core manifest base address in x0, which in !RESET_TO_BL31 765 * case loaded after base of non shared SRAM(after 4KB offset of SRAM). But in 766 * RESET_TO_BL31 case all non shared SRAM is allocated to BL31, so to avoid 767 * overwriting of manifest keep it in the last page. 768 */ 769 #define ARM_SPMC_MANIFEST_BASE (ARM_TRUSTED_SRAM_BASE + \ 770 PLAT_ARM_TRUSTED_SRAM_SIZE -\ 771 PAGE_SIZE) 772 #endif 773 774 /******************************************************************************* 775 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 776 ******************************************************************************/ 777 #define BL2U_BASE BL2_BASE 778 #define BL2U_LIMIT BL2_LIMIT 779 780 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 781 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 782 783 /* 784 * ID of the secure physical generic timer interrupt used by the TSP. 785 */ 786 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 787 788 789 /* 790 * One cache line needed for bakery locks on ARM platforms 791 */ 792 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 793 794 /* Priority levels for ARM platforms */ 795 #if ENABLE_FEAT_RAS && FFH_SUPPORT 796 #define PLAT_RAS_PRI 0x10 797 #endif 798 #define PLAT_SDEI_CRITICAL_PRI 0x60 799 #define PLAT_SDEI_NORMAL_PRI 0x70 800 801 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 802 #define PLAT_CORE_FAULT_IRQ 17 803 804 /* ARM platforms use 3 upper bits of secure interrupt priority */ 805 #define PLAT_PRI_BITS 3 806 807 /* SGI used for SDEI signalling */ 808 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 809 810 #if SDEI_IN_FCONF 811 /* ARM SDEI dynamic private event max count */ 812 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 813 814 /* ARM SDEI dynamic shared event max count */ 815 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 816 #else 817 /* ARM SDEI dynamic private event numbers */ 818 #define ARM_SDEI_DP_EVENT_0 1000 819 #define ARM_SDEI_DP_EVENT_1 1001 820 #define ARM_SDEI_DP_EVENT_2 1002 821 822 /* ARM SDEI dynamic shared event numbers */ 823 #define ARM_SDEI_DS_EVENT_0 2000 824 #define ARM_SDEI_DS_EVENT_1 2001 825 #define ARM_SDEI_DS_EVENT_2 2002 826 827 #define ARM_SDEI_PRIVATE_EVENTS \ 828 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 829 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 830 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 831 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 832 833 #define ARM_SDEI_SHARED_EVENTS \ 834 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 835 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 836 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 837 #endif /* SDEI_IN_FCONF */ 838 839 #endif /* ARM_DEF_H */ 840