1# 2# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 4 10 11include plat/st/common/common.mk 12 13ARM_CORTEX_A7 := yes 14ARM_WITH_NEON := yes 15USE_COHERENT_MEM := 0 16 17# Default Device tree 18DTB_FILE_NAME ?= stm32mp157c-ev1.dtb 19 20TF_CFLAGS += -DSTM32MP1X 21 22STM32MP13 ?= 0 23STM32MP15 ?= 0 24 25ifeq ($(STM32MP13),1) 26ifeq ($(STM32MP15),1) 27$(error Cannot enable both flags STM32MP13 and STM32MP15) 28endif 29STM32MP13 := 1 30STM32MP15 := 0 31else ifeq ($(STM32MP15),1) 32STM32MP13 := 0 33STM32MP15 := 1 34else ifneq ($(findstring stm32mp13,$(DTB_FILE_NAME)),) 35STM32MP13 := 1 36STM32MP15 := 0 37else ifneq ($(findstring stm32mp15,$(DTB_FILE_NAME)),) 38STM32MP13 := 0 39STM32MP15 := 1 40endif 41 42ifeq ($(STM32MP13),1) 43# Will use SRAM2 as mbedtls heap 44STM32MP_USE_EXTERNAL_HEAP := 1 45 46# DDR controller with single AXI port and 16-bit interface 47STM32MP_DDR_DUAL_AXI_PORT:= 0 48STM32MP_DDR_32BIT_INTERFACE:= 0 49 50ifeq (${TRUSTED_BOARD_BOOT},1) 51# PKA algo to include 52PKA_USE_NIST_P256 := 1 53PKA_USE_BRAINPOOL_P256T1:= 1 54endif 55 56# STM32 image header version v2.0 57STM32_HEADER_VERSION_MAJOR:= 2 58STM32_HEADER_VERSION_MINOR:= 0 59endif 60 61ifeq ($(STM32MP15),1) 62# DDR controller with dual AXI port and 32-bit interface 63STM32MP_DDR_DUAL_AXI_PORT:= 1 64STM32MP_DDR_32BIT_INTERFACE:= 1 65 66# STM32 image header version v1.0 67STM32_HEADER_VERSION_MAJOR:= 1 68STM32_HEADER_VERSION_MINOR:= 0 69STM32MP_CRYPTO_ROM_LIB := 1 70 71# Decryption support 72ifneq ($(DECRYPTION_SUPPORT),none) 73$(error "DECRYPTION_SUPPORT not supported on STM32MP15") 74endif 75endif 76 77PKA_USE_NIST_P256 ?= 0 78PKA_USE_BRAINPOOL_P256T1 ?= 0 79 80ifeq ($(AARCH32_SP),sp_min) 81# Disable Neon support: sp_min runtime may conflict with non-secure world 82TF_CFLAGS += -mfloat-abi=soft 83endif 84 85# Not needed for Cortex-A7 86WORKAROUND_CVE_2017_5715:= 0 87WORKAROUND_CVE_2022_23960:= 0 88 89ifeq ($(STM32MP13),1) 90STM32_HASH_VER := 4 91STM32_RNG_VER := 4 92else # Assuming STM32MP15 93STM32_HASH_VER := 2 94STM32_RNG_VER := 2 95endif 96 97# Download load address for serial boot devices 98DWL_BUFFER_BASE ?= 0xC7000000 99 100# Device tree 101ifeq ($(STM32MP13),1) 102BL2_DTSI := stm32mp13-bl2.dtsi 103FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 104else 105BL2_DTSI := stm32mp15-bl2.dtsi 106FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 107ifeq ($(AARCH32_SP),sp_min) 108BL32_DTSI := stm32mp15-bl32.dtsi 109FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME))) 110ifneq (,$(wildcard $(patsubst %.dtb,fdts/%-sp_min.dts,$(DTB_FILE_NAME)))) 111ifeq (,$(findstring -sp_min,$(DTB_FILE_NAME))) 112SP_EXT := -sp_min 113endif 114endif 115endif 116endif 117 118# Macros and rules to build TF binary 119STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 120STM32_LD_FILE := plat/st/stm32mp1/stm32mp1.ld.S 121STM32_BINARY_MAPPING := plat/st/stm32mp1/stm32mp1.S 122 123ifeq ($(AARCH32_SP),sp_min) 124# BL32 is built only if using SP_MIN 125BL32_DEP := bl32 126ASFLAGS += -DBL32_BIN_PATH=\"${BUILD_PLAT}/bl32.bin\" 127endif 128 129STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 130STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 131ifneq (${AARCH32_SP},none) 132FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 133endif 134# Add the FW_CONFIG to FIP and specify the same to certtool 135$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 136ifeq ($(GENERATE_COT),1) 137STM32MP_CFG_CERT := $(BUILD_PLAT)/stm32mp_cfg_cert.crt 138# Add the STM32MP_CFG_CERT to FIP and specify the same to certtool 139$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_CFG_CERT},--stm32mp-cfg-cert)) 140endif 141ifeq ($(AARCH32_SP),sp_min) 142STM32MP_TOS_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dtb,$(DTB_FILE_NAME))) 143$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_TOS_FW_CONFIG},--tos-fw-config)) 144endif 145 146# Enable flags for C files 147$(eval $(call assert_booleans,\ 148 $(sort \ 149 PKA_USE_BRAINPOOL_P256T1 \ 150 PKA_USE_NIST_P256 \ 151 STM32MP_CRYPTO_ROM_LIB \ 152 STM32MP_DDR_32BIT_INTERFACE \ 153 STM32MP_DDR_DUAL_AXI_PORT \ 154 STM32MP_USE_EXTERNAL_HEAP \ 155 STM32MP13 \ 156 STM32MP15 \ 157))) 158 159$(eval $(call assert_numerics,\ 160 $(sort \ 161 PLAT_PARTITION_MAX_ENTRIES \ 162 STM32_HASH_VER \ 163 STM32_HEADER_VERSION_MAJOR \ 164 STM32_RNG_VER \ 165 STM32_TF_A_COPIES \ 166))) 167 168$(eval $(call add_defines,\ 169 $(sort \ 170 DWL_BUFFER_BASE \ 171 PKA_USE_BRAINPOOL_P256T1 \ 172 PKA_USE_NIST_P256 \ 173 PLAT_PARTITION_MAX_ENTRIES \ 174 PLAT_TBBR_IMG_DEF \ 175 STM32_HASH_VER \ 176 STM32_HEADER_VERSION_MAJOR \ 177 STM32_RNG_VER \ 178 STM32_TF_A_COPIES \ 179 STM32MP_CRYPTO_ROM_LIB \ 180 STM32MP_DDR_32BIT_INTERFACE \ 181 STM32MP_DDR_DUAL_AXI_PORT \ 182 STM32MP_USE_EXTERNAL_HEAP \ 183 STM32MP13 \ 184 STM32MP15 \ 185))) 186 187# Include paths and source files 188PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ 189 190PLAT_BL_COMMON_SOURCES += plat/st/stm32mp1/stm32mp1_private.c 191 192PLAT_BL_COMMON_SOURCES += drivers/st/uart/aarch32/stm32_console.S 193 194ifneq (${ENABLE_STACK_PROTECTOR},0) 195PLAT_BL_COMMON_SOURCES += plat/st/stm32mp1/stm32mp1_stack_protector.c 196endif 197 198PLAT_BL_COMMON_SOURCES += lib/cpus/aarch32/cortex_a7.S 199 200PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ 201 drivers/st/bsec/bsec2.c \ 202 drivers/st/ddr/stm32mp1_ddr_helpers.c \ 203 drivers/st/i2c/stm32_i2c.c \ 204 drivers/st/iwdg/stm32_iwdg.c \ 205 drivers/st/pmic/stm32mp_pmic.c \ 206 drivers/st/pmic/stpmic1.c \ 207 drivers/st/reset/stm32mp1_reset.c \ 208 plat/st/stm32mp1/stm32mp1_dbgmcu.c \ 209 plat/st/stm32mp1/stm32mp1_helper.S \ 210 plat/st/stm32mp1/stm32mp1_syscfg.c 211 212ifeq ($(STM32MP13),1) 213PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 214 drivers/st/clk/clk-stm32mp13.c \ 215 drivers/st/crypto/stm32_rng.c 216else 217PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c 218endif 219 220BL2_SOURCES += plat/st/stm32mp1/plat_bl2_mem_params_desc.c \ 221 plat/st/stm32mp1/stm32mp1_fconf_firewall.c 222 223BL2_SOURCES += drivers/st/crypto/stm32_hash.c \ 224 plat/st/stm32mp1/bl2_plat_setup.c 225 226ifeq (${TRUSTED_BOARD_BOOT},1) 227ifeq ($(STM32MP13),1) 228BL2_SOURCES += drivers/st/crypto/stm32_pka.c 229BL2_SOURCES += drivers/st/crypto/stm32_saes.c 230endif 231endif 232 233ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 234BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 235endif 236 237ifeq (${STM32MP_RAW_NAND},1) 238BL2_SOURCES += drivers/st/fmc/stm32_fmc2_nand.c 239endif 240 241ifneq ($(filter 1,${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),) 242BL2_SOURCES += drivers/st/spi/stm32_qspi.c 243endif 244 245ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND} ${STM32MP_SPI_NOR}),) 246BL2_SOURCES += plat/st/stm32mp1/stm32mp1_boot_device.c 247endif 248 249ifeq (${STM32MP_UART_PROGRAMMER},1) 250BL2_SOURCES += drivers/st/uart/stm32_uart.c 251endif 252 253ifeq (${STM32MP_USB_PROGRAMMER},1) 254#The DFU stack uses only one end point, reduce the USB stack footprint 255$(eval $(call add_define_val,CONFIG_USBD_EP_NB,1U)) 256BL2_SOURCES += drivers/st/usb/stm32mp1_usb.c \ 257 plat/st/stm32mp1/stm32mp1_usb_dfu.c 258endif 259 260BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \ 261 drivers/st/ddr/stm32mp1_ram.c 262 263BL2_SOURCES += plat/st/stm32mp1/plat_ddr.c 264 265ifeq ($(AARCH32_SP),sp_min) 266# Create DTB file for BL32 267${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | $$(@D)/ 268 $(q)echo '#include "$(patsubst %.dts,%$(SP_EXT).dts,$(patsubst fdts/%,%,$<))"' > $@ 269 $(q)echo '#include "${BL32_DTSI}"' >> $@ 270 271${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts | $$(@D)/ 272endif 273 274include plat/st/common/common_rules.mk 275