1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. 34ifeq (${ENABLE_RME},1) 35FVP_TRUSTED_SRAM_SIZE := 384 36else 37FVP_TRUSTED_SRAM_SIZE := 256 38endif 39 40# Macro to enable helpers for running SPM tests. Disabled by default. 41PLAT_TEST_SPM := 0 42 43# By default dont build CPUs with no FVP model. 44BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 45 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52 53ifeq (${ARCH}, aarch64) 54 55ifeq (${SPM_MM}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58 ENABLE_SME2_FOR_NS := 2 59else 60 ENABLE_SVE_FOR_NS := 0 61 ENABLE_SME_FOR_NS := 0 62 ENABLE_SME2_FOR_NS := 0 63endif 64endif 65 66 ENABLE_BRBE_FOR_NS := 2 67 ENABLE_TRBE_FOR_NS := 2 68 ENABLE_FEAT_D128 := 2 69 ENABLE_FEAT_FPMR := 2 70 ENABLE_FEAT_MOPS := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_DEBUGV8P9 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_FGT2 := 2 86ENABLE_FEAT_THE := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92ENABLE_FEAT_SCTLR2 := 2 93ENABLE_FEAT_MTE2 := 2 94ENABLE_FEAT_LS64_ACCDATA := 2 95 96# The FVP platform depends on this macro to build with correct GIC driver. 97$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 98 99# Pass FVP_CLUSTER_COUNT to the build system. 100$(eval $(call add_define,FVP_CLUSTER_COUNT)) 101 102# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 103$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 104 105# Pass FVP_MAX_PE_PER_CPU to the build system. 106$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 107 108# Pass FVP_GICR_REGION_PROTECTION to the build system. 109$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 110 111# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 112$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 113 114# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 115# choose the CCI driver , else the CCN driver 116ifeq ($(FVP_CLUSTER_COUNT), 0) 117$(error "Incorrect cluster count specified for FVP port") 118else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 119FVP_INTERCONNECT_DRIVER := FVP_CCI 120else 121FVP_INTERCONNECT_DRIVER := FVP_CCN 122endif 123 124$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 125 126# Choose the GIC sources depending upon the how the FVP will be invoked 127ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 128 129# The GIC model (GIC-600 or GIC-500) will be detected at runtime 130GICV3_SUPPORT_GIC600 := 1 131GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 132 133# Include GICv3 driver files 134include drivers/arm/gic/v3/gicv3.mk 135 136FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 137 plat/common/plat_gicv3.c \ 138 plat/arm/common/arm_gicv3.c 139 140 ifeq ($(filter 1,${RESET_TO_BL2} \ 141 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 142 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 143 endif 144 145else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 146 147# No GICv4 extension 148GIC_ENABLE_V4_EXTN := 0 149$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 150 151# Include GICv2 driver files 152include drivers/arm/gic/v2/gicv2.mk 153 154FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 155 plat/common/plat_gicv2.c \ 156 plat/arm/common/arm_gicv2.c 157 158FVP_DT_PREFIX := fvp-base-gicv2-psci 159else 160$(error "Incorrect GIC driver chosen on FVP port") 161endif 162 163ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 164FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 165else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 166FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 167 plat/arm/common/arm_ccn.c 168else 169$(error "Incorrect CCN driver chosen on FVP port") 170endif 171 172FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 173 plat/arm/board/fvp/fvp_security.c \ 174 plat/arm/common/arm_tzc400.c 175 176 177PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 178 -Iinclude/lib/psa 179 180 181PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 182 183FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 184 185ifeq (${ARCH}, aarch64) 186 187# select a different set of CPU files, depending on whether we compile for 188# hardware assisted coherency cores or not 189ifeq (${HW_ASSISTED_COHERENCY}, 0) 190# Cores used without DSU 191 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 192 lib/cpus/aarch64/cortex_a53.S \ 193 lib/cpus/aarch64/cortex_a57.S \ 194 lib/cpus/aarch64/cortex_a72.S \ 195 lib/cpus/aarch64/cortex_a73.S 196else 197# Cores used with DSU only 198 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 199 # AArch64-only cores 200 # TODO: add all cores to the appropriate lists 201 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 202 lib/cpus/aarch64/cortex_a65ae.S \ 203 lib/cpus/aarch64/cortex_a76.S \ 204 lib/cpus/aarch64/cortex_a76ae.S \ 205 lib/cpus/aarch64/cortex_a77.S \ 206 lib/cpus/aarch64/cortex_a78.S \ 207 lib/cpus/aarch64/cortex_a78_ae.S \ 208 lib/cpus/aarch64/cortex_a78c.S \ 209 lib/cpus/aarch64/cortex_a710.S \ 210 lib/cpus/aarch64/cortex_a715.S \ 211 lib/cpus/aarch64/cortex_a720.S \ 212 lib/cpus/aarch64/cortex_a720_ae.S \ 213 lib/cpus/aarch64/neoverse_n1.S \ 214 lib/cpus/aarch64/neoverse_n2.S \ 215 lib/cpus/aarch64/neoverse_v1.S \ 216 lib/cpus/aarch64/neoverse_e1.S \ 217 lib/cpus/aarch64/cortex_x2.S \ 218 lib/cpus/aarch64/cortex_x4.S 219 endif 220 # AArch64/AArch32 cores 221 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 222 lib/cpus/aarch64/cortex_a75.S 223endif 224 225#Include all CPUs to build to support all-errata build. 226ifeq (${ENABLE_ERRATA_ALL},1) 227 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 228 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ 229 lib/cpus/aarch64/cortex_a520.S \ 230 lib/cpus/aarch64/cortex_a725.S \ 231 lib/cpus/aarch64/cortex_x1.S \ 232 lib/cpus/aarch64/cortex_x3.S \ 233 lib/cpus/aarch64/cortex_x925.S \ 234 lib/cpus/aarch64/neoverse_n3.S \ 235 lib/cpus/aarch64/neoverse_v2.S \ 236 lib/cpus/aarch64/neoverse_v3.S 237endif 238 239#Build AArch64-only CPUs with no FVP model yet. 240ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 241 # travis/gelas need these 242 FEAT_PABANDON := 1 243 ERRATA_SME_POWER_DOWN := 1 244 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 245 lib/cpus/aarch64/cortex_gelas.S \ 246 lib/cpus/aarch64/nevis.S \ 247 lib/cpus/aarch64/travis.S \ 248 lib/cpus/aarch64/cortex_arcadia.S \ 249 lib/cpus/aarch64/cortex_alto.S 250endif 251 252else 253FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 254 lib/cpus/aarch32/cortex_a57.S \ 255 lib/cpus/aarch32/cortex_a53.S 256endif 257 258BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 259 drivers/arm/sp805/sp805.c \ 260 drivers/delay_timer/delay_timer.c \ 261 drivers/io/io_semihosting.c \ 262 lib/semihosting/semihosting.c \ 263 lib/semihosting/${ARCH}/semihosting_call.S \ 264 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 265 plat/arm/board/fvp/fvp_bl1_setup.c \ 266 plat/arm/board/fvp/fvp_cpu_pwr.c \ 267 plat/arm/board/fvp/fvp_err.c \ 268 plat/arm/board/fvp/fvp_io_storage.c \ 269 plat/arm/board/fvp/fvp_topology.c \ 270 ${FVP_CPU_LIBS} \ 271 ${FVP_INTERCONNECT_SOURCES} 272 273ifeq (${USE_SP804_TIMER},1) 274BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 275else 276BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 277endif 278 279 280BL2_SOURCES += drivers/arm/sp805/sp805.c \ 281 drivers/io/io_semihosting.c \ 282 lib/utils/mem_region.c \ 283 lib/semihosting/semihosting.c \ 284 lib/semihosting/${ARCH}/semihosting_call.S \ 285 plat/arm/board/fvp/fvp_bl2_setup.c \ 286 plat/arm/board/fvp/fvp_err.c \ 287 plat/arm/board/fvp/fvp_io_storage.c \ 288 plat/arm/common/arm_nor_psci_mem_protect.c \ 289 ${FVP_SECURITY_SOURCES} 290 291 292ifeq (${COT_DESC_IN_DTB},1) 293BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 294endif 295 296ifeq (${ENABLE_RME},1) 297BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 298 plat/arm/board/fvp/fvp_cpu_pwr.c 299 300BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 301 plat/arm/board/fvp/fvp_realm_attest_key.c \ 302 plat/arm/board/fvp/fvp_el3_token_sign.c 303endif 304 305ifeq (${ENABLE_FEAT_RNG_TRAP},1) 306BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 307endif 308 309ifeq (${RESET_TO_BL2},1) 310BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 311 plat/arm/board/fvp/fvp_cpu_pwr.c \ 312 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 313 ${FVP_CPU_LIBS} \ 314 ${FVP_INTERCONNECT_SOURCES} 315endif 316 317ifeq (${USE_SP804_TIMER},1) 318BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 319endif 320 321BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 322 ${FVP_SECURITY_SOURCES} 323 324ifeq (${USE_SP804_TIMER},1) 325BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 326endif 327 328BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 329 drivers/arm/smmu/smmu_v3.c \ 330 drivers/delay_timer/delay_timer.c \ 331 drivers/cfi/v2m/v2m_flash.c \ 332 lib/utils/mem_region.c \ 333 plat/arm/board/fvp/fvp_bl31_setup.c \ 334 plat/arm/board/fvp/fvp_console.c \ 335 plat/arm/board/fvp/fvp_pm.c \ 336 plat/arm/board/fvp/fvp_topology.c \ 337 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 338 plat/arm/board/fvp/fvp_cpu_pwr.c \ 339 plat/arm/common/arm_nor_psci_mem_protect.c \ 340 ${FVP_CPU_LIBS} \ 341 ${FVP_GIC_SOURCES} \ 342 ${FVP_INTERCONNECT_SOURCES} \ 343 ${FVP_SECURITY_SOURCES} 344 345# Support for fconf in BL31 346# Added separately from the above list for better readability 347ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 348BL31_SOURCES += lib/fconf/fconf.c \ 349 lib/fconf/fconf_dyn_cfg_getter.c \ 350 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 351 352BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 353 354ifeq (${SEC_INT_DESC_IN_FCONF},1) 355BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 356endif 357 358endif 359 360ifeq (${USE_SP804_TIMER},1) 361BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 362else 363BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 364endif 365 366# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 367FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 368 369FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 370$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 371 372ifeq (${TRANSFER_LIST}, 0) 373FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 374 ${PLAT}_fw_config.dts \ 375 ${PLAT}_tb_fw_config.dts \ 376 ${PLAT}_soc_fw_config.dts \ 377 ${PLAT}_nt_fw_config.dts \ 378 ) 379 380FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 381FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 382FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 383FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 384 385ifeq (${SPD},tspd) 386FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 387FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 388 389# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 390$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 391endif 392 393ifeq (${SPD},spmd) 394 395ifeq ($(ARM_SPMC_MANIFEST_DTS),) 396ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 397endif 398 399FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 400FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 401 402# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 403$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 404endif 405 406# Add the FW_CONFIG to FIP and specify the same to certtool 407$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 408# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 409$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 410# Add the NT_FW_CONFIG to FIP and specify the same to certtool 411$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 412# Add the TB_FW_CONFIG to FIP and specify the same to certtool 413$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 414endif 415 416# Add the HW_CONFIG to FIP and specify the same to certtool 417$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 418 419ifeq (${TRANSFER_LIST}, 1) 420include lib/transfer_list/transfer_list.mk 421 422ifeq ($(RESET_TO_BL31), 1) 423HW_CONFIG := ${FVP_HW_CONFIG} 424FW_HANDOFF_SIZE := 20000 425 426TRANSFER_LIST_DTB_OFFSET := 0x20 427$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 428endif 429endif 430 431ifeq (${HOB_LIST}, 1) 432include lib/hob/hob.mk 433endif 434 435# Enable dynamic mitigation support by default 436DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 437 438ifneq (${ENABLE_FEAT_AMU},0) 439BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 440 lib/cpus/aarch64/cpuamu_helpers.S 441 442ifeq (${HW_ASSISTED_COHERENCY}, 1) 443BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 444 lib/cpus/aarch64/neoverse_n1_pubsub.c 445endif 446endif 447 448ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 449 ifeq (${ENABLE_FEAT_RAS},1) 450 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 451 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 452 else 453 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 454 endif 455 else 456 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 457 endif 458endif 459 460ifneq (${ENABLE_STACK_PROTECTOR},0) 461PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 462endif 463 464# Enable the dynamic translation tables library. 465ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 466 ifeq (${ARCH},aarch32) 467 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 468 else # AArch64 469 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 470 endif 471endif 472 473ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 474 ifeq (${ARCH},aarch32) 475 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 476 else # AArch64 477 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 478 ifeq (${SPD},tspd) 479 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 480 endif 481 endif 482endif 483 484ifeq (${USE_DEBUGFS},1) 485 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 486endif 487 488# Add support for platform supplied linker script for BL31 build 489$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 490 491ifneq (${RESET_TO_BL2}, 0) 492 override BL1_SOURCES = 493endif 494 495include plat/arm/board/common/board_common.mk 496include plat/arm/common/arm_common.mk 497 498ifeq (${MEASURED_BOOT},1) 499BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 500 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 501 lib/psa/measured_boot.c 502 503BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 504 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 505 lib/psa/measured_boot.c 506endif 507 508ifeq (${DRTM_SUPPORT}, 1) 509BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 510 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 511 plat/arm/board/fvp/fvp_drtm_err.c \ 512 plat/arm/board/fvp/fvp_drtm_measurement.c \ 513 plat/arm/board/fvp/fvp_drtm_stub.c \ 514 plat/arm/common/arm_dyn_cfg.c \ 515 plat/arm/board/fvp/fvp_err.c 516endif 517 518ifeq (${TRUSTED_BOARD_BOOT}, 1) 519BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 520BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 521 522# FVP being a development platform, enable capability to disable Authentication 523# dynamically if TRUSTED_BOARD_BOOT is set. 524DYN_DISABLE_AUTH := 1 525endif 526 527ifeq (${SPMC_AT_EL3}, 1) 528PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 529endif 530 531PSCI_OS_INIT_MODE := 1 532 533ifeq (${SPD},spmd) 534BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 535endif 536 537# Test specific macros, keep them at bottom of this file 538$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 539ifeq (${PLATFORM_TEST_EA_FFH}, 1) 540 ifeq (${FFH_SUPPORT}, 0) 541 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 542 endif 543 544endif 545 546$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 547ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 548 ifeq (${ENABLE_FEAT_RAS}, 0) 549 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 550 endif 551 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 552 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 553 endif 554endif 555 556$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 557ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 558 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 559 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 560 endif 561 ifeq (${ENABLE_SPMD_LP}, 0) 562 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 563 endif 564 ifeq (${ENABLE_FEAT_RAS}, 0) 565 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 566 endif 567 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 568 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 569 endif 570endif 571 572ifeq (${ERRATA_ABI_SUPPORT}, 1) 573include plat/arm/board/fvp/fvp_cpu_errata.mk 574endif 575 576# Build macro necessary for running SPM tests on FVP platform 577$(eval $(call add_define,PLAT_TEST_SPM)) 578