1 /* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/arm/gicv5.h> 8 #include <platform_def.h> 9 10 /* wire 26 is the timer interrupt. Will be assigned NS by default */ 11 struct gicv5_wire_props irs0_spis[] = { 12 }; 13 14 struct gicv5_wire_props iwb0_wires[] = { 15 }; 16 17 struct gicv5_irs irss[] = {{ 18 .el3_config_frame = BASE_IRS_BASE, 19 .spis = irs0_spis, 20 .num_spis = ARRAY_SIZE(irs0_spis), 21 }}; 22 23 struct gicv5_iwb iwbs[] = {{ 24 .config_frame = BASE_IWB_BASE, 25 .wires = iwb0_wires, 26 .num_wires = ARRAY_SIZE(iwb0_wires) 27 }}; 28 29 const struct gicv5_driver_data plat_gicv5_driver_data = { 30 .irss = irss, 31 .iwbs = iwbs, 32 .num_irss = ARRAY_SIZE(irss), 33 .num_iwbs = ARRAY_SIZE(iwbs) 34 }; 35 36 void fvp_gic_driver_pre_init(void) 37 { 38 } 39 40 void fvp_pcpu_init(void) 41 { 42 } 43