1# Copyright (c) 2021-2025, Arm Limited. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6include common/fdt_wrappers.mk 7 8TARGET_FLAVOUR := fvp 9# DPU with SCMI may not necessarily work, so allow its independence 10TC_DPU_USE_SCMI_CLK := 1 11# SCMI power domain control enable 12TC_SCMI_PD_CTRL_EN := 1 13 14# System setup 15CSS_USE_SCMI_SDS_DRIVER := 1 16HW_ASSISTED_COHERENCY := 1 17USE_COHERENT_MEM := 0 18USE_GIC_DRIVER := 3 19USE_DSU_DRIVER := 1 20GIC_ENABLE_V4_EXTN := 1 21GICV3_SUPPORT_GIC600 := 1 22override NEED_BL2U := no 23override ARM_PLAT_MT := 1 24 25# CPU setup 26ARM_ARCH_MINOR := 7 27BRANCH_PROTECTION := 1 28ENABLE_FEAT_MPAM := 1 # default is 2, optimise 29ENABLE_SVE_FOR_NS := 2 # to show we use it 30ENABLE_SVE_FOR_SWD := 1 31ENABLE_SME_FOR_NS := 2 32ENABLE_SME2_FOR_NS := 2 33ENABLE_SME_FOR_SWD := 1 34ENABLE_TRBE_FOR_NS := 1 35ENABLE_SYS_REG_TRACE_FOR_NS := 1 36ENABLE_FEAT_AMU := 1 37ENABLE_AMU_AUXILIARY_COUNTERS := 1 38ENABLE_MPMM := 1 39ENABLE_FEAT_MTE2 := 2 40ENABLE_SPE_FOR_NS := 2 41ENABLE_FEAT_TCR2 := 2 42 43ifneq ($(filter ${TARGET_PLATFORM}, 3),) 44ENABLE_FEAT_RNG_TRAP := 0 45else 46ENABLE_FEAT_RNG_TRAP := 1 47endif 48 49CTX_INCLUDE_AARCH32_REGS := 0 50 51ifeq (${SPD},spmd) 52 SPMD_SPM_AT_SEL2 := 1 53 CTX_INCLUDE_PAUTH_REGS := 1 54endif 55 56TRNG_SUPPORT := 1 57 58# TC RESOLUTION - LIST OF VALID OPTIONS (this impacts only FVP) 59TC_RESOLUTION_OPTIONS := 640x480p60 \ 60 1920x1080p60 61# Set default to the 640x480p60 resolution mode 62TC_RESOLUTION ?= $(firstword $(TC_RESOLUTION_OPTIONS)) 63 64# Check resolution option for FVP 65ifneq ($(filter ${TARGET_FLAVOUR}, fvp),) 66ifeq ($(filter ${TC_RESOLUTION}, ${TC_RESOLUTION_OPTIONS}),) 67 $(error TC_RESOLUTION is ${TC_RESOLUTION}, it must be: ${TC_RESOLUTION_OPTIONS}) 68endif 69endif 70 71ifneq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0) 72 $(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.) 73endif 74 75ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0) 76 $(error TARGET_PLATFORM must be less than or equal to 4) 77endif 78 79ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),) 80 $(error TARGET_FLAVOUR must be fvp or fpga) 81endif 82 83# Support for loading FS Image to DRAM 84TC_FPGA_FS_IMG_IN_RAM := 0 85 86# Support Loading of FIP image to DRAM 87TC_FPGA_FIP_IMG_IN_RAM := 0 88 89# Use simple panel instead of vencoder with DPU 90TC_DPU_USE_SIMPLE_PANEL := 0 91 92$(eval $(call add_defines, \ 93 TARGET_PLATFORM \ 94 TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \ 95 TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \ 96 TC_DPU_USE_SCMI_CLK \ 97 TC_SCMI_PD_CTRL_EN \ 98 TC_FPGA_FS_IMG_IN_RAM \ 99 TC_FPGA_FIP_IMG_IN_RAM \ 100 TC_DPU_USE_SIMPLE_PANEL \ 101)) 102 103CSS_LOAD_SCP_IMAGES := 1 104 105# Save DSU PMU registers on cluster off and restore them on cluster on 106PRESERVE_DSU_PMU_REGS := 1 107 108PLAT_MHU := MHUv3 109 110TC_BASE = plat/arm/board/tc 111 112PLAT_INCLUDES += -I${TC_BASE}/include/ \ 113 -I${TC_BASE}/fdts/ 114 115# CPU libraries for TARGET_PLATFORM=3 116ifeq (${TARGET_PLATFORM}, 3) 117ERRATA_A520_2938996 := 1 118 119TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ 120 lib/cpus/aarch64/cortex_a725.S \ 121 lib/cpus/aarch64/cortex_x925.S 122endif 123 124# CPU libraries for TARGET_PLATFORM=4 125ifeq (${TARGET_PLATFORM}, 4) 126FEAT_PABANDON := 1 127# prevent CME related wakups 128ERRATA_SME_POWER_DOWN := 1 129TC_CPU_SOURCES += lib/cpus/aarch64/cortex_gelas.S \ 130 lib/cpus/aarch64/nevis.S \ 131 lib/cpus/aarch64/travis.S 132endif 133 134INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \ 135 plat/arm/common/arm_ni.c 136 137PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \ 138 ${TC_BASE}/include/tc_helpers.S 139 140 141ifneq (${ENABLE_STACK_PROTECTOR},0) 142PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_stack_protector.c 143endif 144 145BL1_SOURCES += ${INTERCONNECT_SOURCES} \ 146 ${TC_CPU_SOURCES} \ 147 ${TC_BASE}/tc_trusted_boot.c \ 148 ${TC_BASE}/tc_bl1_setup.c \ 149 ${TC_BASE}/tc_err.c \ 150 drivers/arm/sbsa/sbsa.c 151 152BL2_SOURCES += ${TC_BASE}/tc_security.c \ 153 ${TC_BASE}/tc_err.c \ 154 ${TC_BASE}/tc_trusted_boot.c \ 155 ${TC_BASE}/tc_bl2_setup.c \ 156 lib/utils/mem_region.c \ 157 drivers/arm/tzc/tzc400.c \ 158 plat/arm/common/arm_nor_psci_mem_protect.c 159 160BL31_SOURCES += ${INTERCONNECT_SOURCES} \ 161 ${TC_CPU_SOURCES} \ 162 ${TC_BASE}/tc_bl31_setup.c \ 163 ${TC_BASE}/tc_topology.c \ 164 lib/fconf/fconf.c \ 165 lib/fconf/fconf_dyn_cfg_getter.c \ 166 drivers/arm/dsu/dsu.c \ 167 drivers/cfi/v2m/v2m_flash.c \ 168 lib/utils/mem_region.c \ 169 plat/arm/common/arm_nor_psci_mem_protect.c \ 170 drivers/arm/sbsa/sbsa.c 171 172BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 173 174# Add the FDT_SOURCES and options for Dynamic Config 175FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \ 176 ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts \ 177 ${TC_BASE}/fdts/${PLAT}_nt_fw_config.dts 178FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 179TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 180FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 181 182# Add the FW_CONFIG to FIP and specify the same to certtool 183$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 184# Add the TB_FW_CONFIG to FIP and specify the same to certtool 185$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 186# Add the NT_FW_CONFIG to FIP and specify the same to certtool 187$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 188 189ifeq (${SPD},spmd) 190ifeq ($(ARM_SPMC_MANIFEST_DTS),) 191ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_test_manifest.dts 192endif 193 194FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 195TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 196 197# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 198$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG})) 199endif 200 201#Device tree 202TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts 203TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 204FDT_SOURCES += ${TC_HW_CONFIG_DTS} 205$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) 206 207# Add the HW_CONFIG to FIP and specify the same to certtool 208$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG})) 209 210$(info Including rse_comms.mk) 211include drivers/arm/rse/rse_comms.mk 212 213BL1_SOURCES += ${RSE_COMMS_SOURCES} \ 214 plat/arm/board/tc/tc_rse_comms.c 215BL2_SOURCES += ${RSE_COMMS_SOURCES} \ 216 plat/arm/board/tc/tc_rse_comms.c 217BL31_SOURCES += ${RSE_COMMS_SOURCES} \ 218 plat/arm/board/tc/tc_rse_comms.c \ 219 lib/psa/rse_platform.c 220 221# Include Measured Boot makefile before any Crypto library makefile. 222# Crypto library makefile may need default definitions of Measured Boot build 223# flags present in Measured Boot makefile. 224ifeq (${MEASURED_BOOT},1) 225 ifeq (${DICE_PROTECTION_ENVIRONMENT},1) 226 $(info Including qcbor.mk) 227 include drivers/measured_boot/rse/qcbor.mk 228 $(info Including dice_prot_env.mk) 229 include drivers/measured_boot/rse/dice_prot_env.mk 230 231 BL1_SOURCES += ${QCBOR_SOURCES} \ 232 ${DPE_SOURCES} \ 233 plat/arm/board/tc/tc_common_dpe.c \ 234 plat/arm/board/tc/tc_bl1_dpe.c \ 235 lib/psa/dice_protection_environment.c \ 236 drivers/arm/css/sds/sds.c \ 237 drivers/delay_timer/delay_timer.c \ 238 drivers/delay_timer/generic_delay_timer.c 239 240 BL2_SOURCES += ${QCBOR_SOURCES} \ 241 ${DPE_SOURCES} \ 242 plat/arm/board/tc/tc_common_dpe.c \ 243 plat/arm/board/tc/tc_bl2_dpe.c \ 244 lib/psa/dice_protection_environment.c 245 246 PLAT_INCLUDES += -I${QCBOR_INCLUDES} \ 247 -Iinclude/lib/dice 248 else 249 $(info Including rse_measured_boot.mk) 250 include drivers/measured_boot/rse/rse_measured_boot.mk 251 252 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \ 253 plat/arm/board/tc/tc_common_measured_boot.c \ 254 plat/arm/board/tc/tc_bl1_measured_boot.c \ 255 lib/psa/measured_boot.c 256 257 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} \ 258 plat/arm/board/tc/tc_common_measured_boot.c \ 259 plat/arm/board/tc/tc_bl2_measured_boot.c \ 260 lib/psa/measured_boot.c 261 endif 262endif 263 264BL31_SOURCES += plat/arm/board/tc/tc_trng.c 265 266ifneq (${ENABLE_FEAT_RNG_TRAP},0) 267 BL31_SOURCES += plat/arm/board/tc/tc_rng_trap.c 268endif 269 270ifneq (${PLATFORM_TEST},) 271 # Add this include as first, before arm_common.mk. This is necessary 272 # because arm_common.mk builds Mbed TLS, and platform_test.mk can 273 # change the list of Mbed TLS files that are to be compiled 274 # (LIBMBEDTLS_SRCS). 275 include plat/arm/board/tc/platform_test.mk 276endif 277 278 279include plat/arm/common/arm_common.mk 280include plat/arm/css/common/css_common.mk 281include plat/arm/board/common/board_common.mk 282