| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3399.h | 79 #define KHz 1000 macro
95 #define PERIHP_PCLK_HZ (37500 * KHz)
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| H A D | cru_rv1103b.h | 13 #define KHz 1000 macro
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| H A D | cru_rv1106.h | 13 #define KHz 1000 macro
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| H A D | cru_rk3506.h | 12 #define KHz 1000 macro
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| H A D | cru_rk1808.h | 12 #define KHz 1000 macro
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| H A D | cru_rv1126.h | 13 #define KHz 1000 macro
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| H A D | cru_px30.h | 12 #define KHz 1000 macro
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| H A D | cru_rk3528.h | 11 #define KHz 1000 macro
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| H A D | cru_rk3562.h | 13 #define KHz 1000 macro
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| H A D | cru_rv1126b.h | 13 #define KHz 1000 macro
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| H A D | cru_rk3588.h | 11 #define KHz 1000 macro
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| H A D | cru_rk3568.h | 11 #define KHz 1000 macro
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| H A D | cru_rk3576.h | 11 #define KHz 1000 macro
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/i2c/ |
| H A D | i2c-gpio.txt | 18 It not defined, then default is 5us (~50KHz).
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | exynos4210-universal_c210.dts | 216 regulator-name = "32KHz AP";
221 regulator-name = "32KHz CP";
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| H A D | sun8i-reference-design-tablet.dtsi | 68 * The gsl1680 is rated at 400KHz and it will not work reliable at
69 * 100KHz, this has been confirmed on multiple different q8 tablets.
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| H A D | imx7d.dtsi | 50 /* KHz uV */
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| H A D | rk3036.dtsi | 51 /* KHz uV */
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| H A D | rk3288-phycore-som.dtsi | 134 /* KHz uV */
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3399.c | 314 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
315 #define VCO_MIN_KHZ (800 * (MHz / KHz))
316 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
317 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config()
454 u32 freq_khz = freq_hz / KHz; in pll_para_config()
500 if (best_diff_khz > 4 * (MHz/KHz)) { in pll_para_config()
503 best_diff_khz * KHz); in pll_para_config()
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| H A D | clk_px30.c | 110 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto()
117 u32 rate_khz = drate / KHz; in pll_clk_set_by_auto()
132 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || in pll_clk_set_by_auto()
163 if (best_diff_khz > 4 * (MHz / KHz)) { in pll_clk_set_by_auto()
166 best_diff_khz * KHz); in pll_clk_set_by_auto()
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| H A D | clk_rk3568.c | 1460 return 750 * KHz; in rk3568_sdmmc_get_clk()
1490 case 750 * KHz: in rk3568_sdmmc_set_clk()
1491 case 400 * KHz: in rk3568_sdmmc_set_clk()
1649 return 375 * KHz; in rk3568_emmc_get_clk()
1679 case 400 * KHz: in rk3568_emmc_set_clk()
1680 case 375 * KHz: in rk3568_emmc_set_clk()
2018 return 62500 * KHz; in rk3568_gmac_ptp_ref_get_clk()
2037 case 62500 * KHz: in rk3568_gmac_ptp_ref_set_clk()
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| /rk3399_rockchip-uboot/drivers/pwm/ |
| H A D | Kconfig | 44 32KHz clock is supported by the driver but the duty cycle is
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | nvidia,tegra20-car.txt | 13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | rockchip_sdhci.c | 25 #define KHz (1000) macro
26 #define MHz (1000 * KHz)
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