| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_cru.c | 62 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
103 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
110 do_div(foutvco, refdiv); in rk628_cru_clk_get_rate_pll()
115 do_div(frac_rate, refdiv); in rk628_cru_clk_get_rate_pll()
132 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
201 for (refdiv = min_refdiv; refdiv <= max_refdiv; refdiv++) { in rk628_cru_clk_set_rate_pll()
204 if (fin % refdiv) in rk628_cru_clk_set_rate_pll()
207 tmp = (u64)fout * refdiv; in rk628_cru_clk_set_rate_pll()
214 do_div(tmp, refdiv); in rk628_cru_clk_set_rate_pll()
221 tmp = (u64)frac_rate * refdiv; in rk628_cru_clk_set_rate_pll()
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| /rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 32 u8 refdiv; member
145 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
154 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
233 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz() local
241 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_cpupll_to_hz()
248 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz() local
256 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_ddrpll_to_hz()
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 132 rate_table->refdiv = fin_hz / clk_gcd; in rockchip_pll_clk_set_by_auto()
140 rate_table->refdiv, in rockchip_pll_clk_set_by_auto()
149 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
152 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
158 fin_64 = fin_64 / (ulong)rate_table->refdiv; in rockchip_pll_clk_set_by_auto()
305 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
332 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); in rk3036_pll_set_rate()
373 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
400 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> in rk3036_pll_get_rate()
407 rate = (p_rate * fbdiv / (refdiv * postdiv1 * postdiv2)) * KHZ; in rk3036_pll_get_rate()
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| H A D | clk_rk3399.c | 36 u32 refdiv; member
49 .refdiv = _refdiv,\
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
358 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
398 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
480 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
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| H A D | clk_rk3036.c | 50 .refdiv = _refdiv,\
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
90 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
234 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rv1108.c | 32 .refdiv = _refdiv,\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
99 (div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_px30.c | 38 .refdiv = _refdiv, \
110 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto() local
143 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_clk_set_by_auto()
144 fref_khz = ref_khz / refdiv; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
228 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
232 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
254 rate->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
272 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
289 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 74 .refdiv = _refdiv, \
98 unsigned int refdiv; member
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| H A D | cru_rk3036.h | 67 u32 refdiv; member
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| H A D | cru_rv1108.h | 55 u32 refdiv; member
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| H A D | cru_rv1103b.h | 119 unsigned int refdiv; member
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| H A D | cru_rv1106.h | 123 unsigned int refdiv; member
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| H A D | cru_rk3506.h | 88 unsigned int refdiv; member
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| H A D | cru_rv1126.h | 143 unsigned int refdiv; member
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| H A D | cru_px30.h | 119 unsigned int refdiv; member
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| H A D | cru_rk3528.h | 109 unsigned int refdiv; member
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| H A D | cru_rk3562.h | 144 unsigned int refdiv; member
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| H A D | cru_rv1126b.h | 148 unsigned int refdiv; member
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| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/ |
| H A D | speed.c | 69 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock() local
72 return (((FREF * pfdr) / refdiv) / busdiv); in get_sys_clock()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 94 pll_priv->refdiv << REFDIV_SHIFT); in pll_set()
132 rk3308_pll_div.refdiv = 2; in rkdclk_init()
142 rk3308_pll_div.refdiv = 2; in rkdclk_init()
150 rk3308_pll_div.refdiv = 2; in rkdclk_init()
186 rk3308_pll_div.refdiv = 1; in rkdclk_init()
194 rk3308_pll_div.refdiv = 6; in rkdclk_init()
263 rk3308_pll_div.refdiv = 2; in rkdclk_init()
326 rk3308_pll_div.refdiv = 6; in rkdclk_init()
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| H A D | sdram_rk3328.c | 79 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
83 refdiv = 1; in rkclk_set_dpll()
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
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| H A D | sdram_px30.c | 78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
82 refdiv = 1; in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
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| H A D | sdram_rv1108.c | 53 params_priv->dpll_init_cfg.refdiv << REFDIV_SHIFT); in rkdclk_init()
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| /rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/ |
| H A D | lowlevel_init.S | 15 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
17 ((0x1F & refdiv) << 16) | \
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| /rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/ |
| H A D | lowlevel_init.S | 20 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
22 ((0x1F & refdiv) << 16) | \
|