| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | inno_video_combo_phy.c | 316 u16 fbdiv; member
411 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
413 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
430 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8)); in inno_mipi_dphy_max_1GHz_pll_enable()
432 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_mipi_dphy_max_1GHz_pll_enable()
666 u16 fbdiv = 28; in inno_video_phy_lvds_mode_enable() local
692 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8)); in inno_video_phy_lvds_mode_enable()
694 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); in inno_video_phy_lvds_mode_enable()
802 u8 *prediv, u16 *fbdiv) in inno_video_phy_pll_round_rate() argument
863 *fbdiv = best_fbdiv; in inno_video_phy_pll_round_rate()
[all …]
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| H A D | rockchip-inno-hdmi-phy.c | 179 u16 fbdiv; member
194 u16 fbdiv; member
602 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); in inno_hdmi_phy_rk3228_power_on()
604 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
678 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | in inno_hdmi_phy_rk3228_pre_pll_update()
682 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
741 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3328_power_on()
745 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
750 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
841 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3328_pre_pll_update()
[all …]
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| H A D | rk618_dsi.c | 214 u16 fbdiv; member
298 u32 fout, fref, prediv, fbdiv; in rk618_dsi_set_hs_clk() local
336 fbdiv = tmp; in rk618_dsi_set_hs_clk()
338 if (fbdiv < 12 || fbdiv > 511) in rk618_dsi_set_hs_clk()
341 if (fbdiv == 15) in rk618_dsi_set_hs_clk()
344 tmp = (u64)fbdiv * fref; in rk618_dsi_set_hs_clk()
351 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
356 phy->fbdiv = fbdiv; in rk618_dsi_set_hs_clk()
400 REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) | in rk618_dsi_phy_power_on()
403 REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv)); in rk618_dsi_phy_power_on()
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| H A D | samsung_mipi_dcphy.c | 231 u16 fbdiv; member
1324 phy_update_bits(samsung, PLL_CON2, M_MASK, M(samsung->pll.fbdiv)); in samsung_mipi_dcphy_pll_configure()
1650 u16 prediv, u16 fbdiv, u8 *mfr, u8 *mrr) in samsung_mipi_dcphy_pll_ssc_modulation_calc() argument
1670 _mrr = (25 * fbdiv << 6) / (_mfr * 100 * 100); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1694 div64_ul(*mfr * *mrr * 1000000, fbdiv << 6)); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1707 u8 *prediv, u16 *fbdiv, u16 *dsm, u8 *scaler, u8 *mfr, u8 *mrr) in samsung_mipi_dcphy_pll_round_rate() argument
1808 *fbdiv = best_fbdiv; in samsung_mipi_dcphy_pll_round_rate()
1825 u16 fbdiv = 0; in samsung_mipi_dcphy_set_pll() local
1831 &fbdiv, &dsm, &scaler, &mfr, &mrr); in samsung_mipi_dcphy_set_pll()
1835 samsung->pll.fbdiv = fbdiv; in samsung_mipi_dcphy_set_pll()
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| H A D | inno_mipi_phy.c | 499 u8 *prediv, u16 *fbdiv) in inno_mipi_dphy_pll_round_rate() argument
534 *fbdiv = best_fbdiv; in inno_mipi_dphy_pll_round_rate()
675 u16 fbdiv = 0; in inno_mipi_dphy_set_pll() local
680 fout = inno_mipi_dphy_pll_round_rate(fin, rate, &prediv, &fbdiv); in inno_mipi_dphy_set_pll()
683 __func__, fin, fout, prediv, fbdiv); in inno_mipi_dphy_set_pll()
686 v = FBDIV_HI(fbdiv >> 8) | PREDIV(prediv); in inno_mipi_dphy_set_pll()
690 v = FBDIV_LO(fbdiv); in inno_mipi_dphy_set_pll()
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3399.c | 37 u32 fbdiv; member
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
354 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
378 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
392 div->fbdiv << PLL_FBDIV_SHIFT); in rkclk_set_pll()
447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
[all …]
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| H A D | clk_pll.c | 133 rate_table->fbdiv = foutvco / clk_gcd; in rockchip_pll_clk_set_by_auto()
141 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
150 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
152 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
305 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
327 rate->fbdiv); in rk3036_pll_set_rate()
373 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
395 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> in rk3036_pll_get_rate()
407 rate = (p_rate * fbdiv / (refdiv * postdiv1 * postdiv2)) * KHZ; in rk3036_pll_get_rate()
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| H A D | clk_rk3036.c | 51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
231 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rv1108.c | 33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
131 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_px30.c | 36 .fbdiv = _fbdiv, \
110 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto() local
146 fbdiv = vco_khz / fref_khz; in pll_clk_set_by_auto()
147 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) in pll_clk_set_by_auto()
149 diff_khz = vco_khz - fbdiv * fref_khz; in pll_clk_set_by_auto()
150 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { in pll_clk_set_by_auto()
151 fbdiv++; in pll_clk_set_by_auto()
160 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
228 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
232 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
[all …]
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_cru.c | 62 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
100 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
109 foutvco = parent_rate * fbdiv; in rk628_cru_clk_get_rate_pll()
133 u16 fbdiv = 0; in rk628_cru_clk_set_rate_pll() local
209 fbdiv = tmp; in rk628_cru_clk_set_rate_pll()
210 if (fbdiv < 10 || fbdiv > 1600) in rk628_cru_clk_set_rate_pll()
213 tmp = (u64)fbdiv * fin; in rk628_cru_clk_set_rate_pll()
240 foutvco = fin * fbdiv; in rk628_cru_clk_set_rate_pll()
256 PLL_FBDIV(fbdiv)); in rk628_cru_clk_set_rate_pll()
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| /rk3399_rockchip-uboot/drivers/video/rockchip/ |
| H A D | rk_mipi.c | 203 u64 fbdiv; in rk_mipi_phy_enable() local
281 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
282 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
286 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
291 test_data[0] = (fbdiv - 1) & 0x1f; in rk_mipi_phy_enable()
293 test_data[0] = (fbdiv - 1) >> 5 | 0x80; in rk_mipi_phy_enable()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 72 .fbdiv = _fbdiv, \
96 unsigned int fbdiv; member
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| H A D | cru_rk3036.h | 68 u32 fbdiv; member
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| H A D | cru_rv1108.h | 56 u32 fbdiv; member
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| H A D | cru_rv1103b.h | 117 unsigned int fbdiv; member
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| H A D | cru_rv1106.h | 121 unsigned int fbdiv; member
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| H A D | cru_rk3506.h | 86 unsigned int fbdiv; member
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| H A D | cru_rv1126.h | 141 unsigned int fbdiv; member
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| H A D | cru_px30.h | 117 unsigned int fbdiv; member
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| H A D | cru_rk3528.h | 107 unsigned int fbdiv; member
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| H A D | cru_rk3562.h | 142 unsigned int fbdiv; member
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 89 pll_priv->fbdiv << FBDIV_SHIFT | in pll_set()
133 rk3308_pll_div.fbdiv = 150; in rkdclk_init()
143 rk3308_pll_div.fbdiv = 262; in rkdclk_init()
151 rk3308_pll_div.fbdiv = 196; in rkdclk_init()
187 rk3308_pll_div.fbdiv = 132; in rkdclk_init()
195 rk3308_pll_div.fbdiv = 325; in rkdclk_init()
264 rk3308_pll_div.fbdiv = 100; in rkdclk_init()
327 rk3308_pll_div.fbdiv = 374; in rkdclk_init()
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| H A D | sdram_rk3328.c | 79 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); in rkclk_set_dpll()
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| H A D | sdram_px30.c | 78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
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