video/drm: phy: dcphy: modify rk3576 data lane driver-down resistor

Signal test to correct dphy DQ driver-down resistors, see
redmine #487592 - #3 for specific report details.

Type: Fix
Redmine ID:

video/drm: phy: dcphy: modify rk3576 data lane driver-down resistor

Signal test to correct dphy DQ driver-down resistors, see
redmine #487592 - #3 for specific report details.

Type: Fix
Redmine ID: #487592
Associated modifications: I3692ce528646ad3b215b212cbb453b0c4c0e9420
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I8761cd94e1639f1531503471889e6adfc38558f1

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video/drm: phy: dcphy: optimize pll and ssc calculation

Type: Fix
Redmine ID: N/A
Associated modifications: If77c1e6526041fdeae07bdc174cddf01bbee4f49
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.h

video/drm: phy: dcphy: optimize pll and ssc calculation

Type: Fix
Redmine ID: N/A
Associated modifications: If77c1e6526041fdeae07bdc174cddf01bbee4f49
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I884fb820ea9b7aef72a03fda7093f579b0f9c015

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video/drm: phy: dcphy: optimize signal

Type: Fix
Redmine ID: #487592
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic504f6a16c1a401698

video/drm: phy: dcphy: optimize signal

Type: Fix
Redmine ID: #487592
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ic504f6a16c1a401698bc066cd7ee2cdbfc7fd9cf

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video/drm: phy: dcphy: add support rk3576

Change-Id: I951d16ea5a0204944730a6c3f181f9e3b908f11c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: phy: dcphy: make Tskewcal maximum is 100 usec at initial calibration

Change-Id: I53c70f5108b2302ab5beed4b2dc9744ef730b913
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: phy: dcphy: fix HSTX_CLK_SEL config

set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps,
while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps

Change-Id: I78138efde39c08337a

video/drm: phy: dcphy: fix HSTX_CLK_SEL config

set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps,
while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps

Change-Id: I78138efde39c08337ae2de0f8098c0fb9435d359
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

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video/drm: phy: dcphy: use m_phy_rst to describe M_RESETN

M_RESETN: reset to PLL、TX Clock lane and data lane 0/1/2/3 block

Change-Id: I532c68361de19d88afefe701692030a284146c57
Signed-off-by: Guochu

video/drm: phy: dcphy: use m_phy_rst to describe M_RESETN

M_RESETN: reset to PLL、TX Clock lane and data lane 0/1/2/3 block

Change-Id: I532c68361de19d88afefe701692030a284146c57
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

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video/drm: phy: dcphy: accurately set mipi channel rate to Kbps/Ksps level

take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi
lane rate should set 445500 Kbps/lane(pclk x bpp = lane_ra

video/drm: phy: dcphy: accurately set mipi channel rate to Kbps/Ksps level

take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi
lane rate should set 445500 Kbps/lane(pclk x bpp = lane_rate x lanes)
when mipi work in no video burst pulse/event, therefore the PLL should
output the rate of Kbps/ksps level for normal display.

Change-Id: Iba0118517462aa71fd18fafc42a0b5c0c190334d
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

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video/drm: phy: dcphy: reduce time when phy power up

Change-Id: If05c651c930167a03ab17484e6cadcc00bfb0e7c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: phy: fix samsung mipi cphy configuration err

Change-Id: I5ed8e59fdb56e4aad915d3956423f5be8cf4a4de
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

video/drm: phy: add samsung mipi dcphy drivers

Change-Id: Ia222750d581421a1b6ffa867b252743c04276a8c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>