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Searched refs:cru (Results 1 – 25 of 171) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1108.c65 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
117 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() argument
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
143 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) in rv1108_mac_set_clk() argument
145 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk()
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
168 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) in rv1108_sfc_set_clk() argument
[all …]
H A Dclk_rk3288.c235 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
239 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
269 static u32 rkclk_pll_get_rate(struct rk3288_cru *cru, in rkclk_pll_get_rate() argument
275 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
282 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
302 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, in rkclk_configure_ddr() argument
332 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
335 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
436 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) in rockchip_mac_set_clk() argument
[all …]
H A Dclk_rk1808.c97 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_get_clk() local
102 con = readl(&cru->pmu_clksel_con[7]); in rk1808_i2c_get_clk()
106 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
110 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
114 con = readl(&cru->clksel_con[60]); in rk1808_i2c_get_clk()
118 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
122 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
136 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_set_clk() local
144 rk_clrsetreg(&cru->pmu_clksel_con[7], in rk1808_i2c_set_clk()
150 rk_clrsetreg(&cru->clksel_con[59], in rk1808_i2c_set_clk()
[all …]
H A Dclk_rk3328.c120 struct rk3328_cru *cru = priv->cru; in rk3328_armclk_set_clk() local
136 priv->cru, NPLL); in rk3328_armclk_set_clk()
139 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
141 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
145 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
150 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
154 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
159 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
163 return rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], priv->cru, NPLL); in rk3328_armclk_set_clk()
169 struct rk3328_cru *cru = priv->cru; in rk3328_i2c_get_clk() local
[all …]
H A Dclk_rk322x.c94 struct rk322x_cru *cru = priv->cru; in rk322x_armclk_set_clk() local
110 priv->cru, APLL); in rk322x_armclk_set_clk()
113 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
115 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
119 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
124 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
133 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
137 return rockchip_pll_get_rate(&rk322x_pll_clks[APLL], priv->cru, APLL); in rk322x_armclk_set_clk()
143 struct rk322x_cru *cru = priv->cru; in rk322x_mmc_get_clk() local
[all …]
H A Dclk_rk3308.c139 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk() local
155 priv->cru, APLL); in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
160 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
168 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
176 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
180 return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL); in rk3308_armclk_set_clk()
187 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
190 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
193 priv->cru, VPLL1); in rk3308_clk_get_pll_rate()
[all …]
H A Dclk_rk3368.c223 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, in rkclk_pll_get_rate() argument
228 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
249 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
252 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
293 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) in rk3368_mmc_get_clk() argument
312 con = readl(&cru->clksel_con[con_id]); in rk3368_mmc_get_clk()
315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
388 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_clk() local
409 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_mmc_set_clk()
[all …]
H A Dclk_rk3036.c62 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
66 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
102 static void rkclk_init(struct rk3036_cru *cru) in rkclk_init() argument
110 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
116 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
117 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
130 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
135 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
153 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
158 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
[all …]
H A Dclk_rk3576.c171 struct rk3576_cru *cru = priv->cru; in rk3576_bus_get_clk() local
176 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
187 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
200 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
220 struct rk3576_cru *cru = priv->cru; in rk3576_bus_set_clk() local
232 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
236 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
252 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
263 rk_clrsetreg(&cru->clksel_con[55], in rk3576_bus_set_clk()
277 struct rk3576_cru *cru = priv->cru; in rk3576_top_get_clk() local
[all …]
H A Dclk_rv1126b.c77 struct rv1126b_cru *cru = priv->cru; in rv1126b_peri_get_clk() local
82 con = readl(&cru->clksel_con[47]); in rv1126b_peri_get_clk()
90 con = readl(&cru->clksel_con[47]); in rv1126b_peri_get_clk()
98 con = readl(&cru->clksel_con[44]); in rv1126b_peri_get_clk()
113 con = readl(&cru->clksel_con[44]); in rv1126b_peri_get_clk()
123 con = readl(&cru->clksel_con[44]); in rv1126b_peri_get_clk()
140 struct rv1126b_cru *cru = priv->cru; in rv1126b_peri_set_clk() local
149 rk_clrsetreg(&cru->clksel_con[47], in rv1126b_peri_set_clk()
158 rk_clrsetreg(&cru->clksel_con[47], in rv1126b_peri_set_clk()
169 rk_clrsetreg(&cru->clksel_con[44], in rv1126b_peri_set_clk()
[all …]
H A Dclk_rk3128.c93 struct rk3128_cru *cru = priv->cru; in rk3128_armclk_set_clk() local
109 priv->cru, APLL); in rk3128_armclk_set_clk()
112 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
114 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_armclk_set_clk()
118 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_armclk_set_clk()
123 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_armclk_set_clk()
127 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_armclk_set_clk()
132 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
136 return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL); in rk3128_armclk_set_clk()
142 struct rk3128_cru *cru = priv->cru; in rockchip_mmc_get_clk() local
[all …]
H A Dclk_rv1103b.c64 struct rv1103b_cru *cru = priv->cru; in rv1103b_peri_get_clk() local
69 con = readl(&cru->clksel_con[31]); in rv1103b_peri_get_clk()
79 con = readl(&cru->clksel_con[31]); in rv1103b_peri_get_clk()
87 con = readl(&cru->peri_clksel_con[0]); in rv1103b_peri_get_clk()
97 con = readl(&cru->pmu_clksel_con[2]); in rv1103b_peri_get_clk()
116 struct rv1103b_cru *cru = priv->cru; in rv1103b_peri_set_clk() local
127 rk_clrsetreg(&cru->clksel_con[31], in rv1103b_peri_set_clk()
136 rk_clrsetreg(&cru->clksel_con[31], in rv1103b_peri_set_clk()
143 rk_clrsetreg(&cru->peri_clksel_con[0], in rv1103b_peri_set_clk()
158 rk_clrsetreg(&cru->pmu_clksel_con[2], in rv1103b_peri_set_clk()
[all …]
H A Dclk_rk3188.c105 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
109 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
139 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_ddr() argument
169 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
172 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); in rkclk_configure_ddr()
179 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
185 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_cpu() argument
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
221 rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); in rkclk_configure_cpu()
228 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
[all …]
H A Dclk_rk3506.c141 sel = (readl(&priv->cru->clksel_con[15]) & in soc_clk_dump()
187 struct rk3506_cru *cru = priv->cru; in rk3506_armclk_get_rate() local
191 con = readl(&cru->clksel_con[15]); in rk3506_armclk_get_rate()
210 struct rk3506_cru *cru = priv->cru; in rk3506_armclk_set_rate() local
225 rk_clrsetreg(&cru->clksel_con[15], ACLK_CORE_DIV_MASK, in rk3506_armclk_set_rate()
227 rk_clrsetreg(&cru->clksel_con[16], PCLK_CORE_DIV_MASK, in rk3506_armclk_set_rate()
246 con = readl(&cru->clksel_con[15]); in rk3506_armclk_set_rate()
249 rk_clrsetreg(&cru->clksel_con[15], CLK_CORE_SRC_DIV_MASK, in rk3506_armclk_set_rate()
251 rk_clrsetreg(&cru->clksel_con[15], CLK_CORE_SRC_SEL_MASK, in rk3506_armclk_set_rate()
254 rk_clrsetreg(&cru->clksel_con[15], CLK_CORE_SRC_SEL_MASK, in rk3506_armclk_set_rate()
[all …]
H A Dclk_rk3588.c153 struct rk3588_cru *cru = priv->cru; in rk3588_center_get_clk() local
158 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
171 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
184 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
197 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
219 struct rk3588_cru *cru = priv->cru; in rk3588_center_set_clk() local
232 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
245 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
258 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
271 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
[all …]
H A Dclk_rv1126.c560 struct rv1126_cru *cru = priv->cru; in rv1126_armclk_set_clk() local
574 priv->cru, APLL); in rv1126_armclk_set_clk()
577 priv->cru, APLL, hz)) in rv1126_armclk_set_clk()
579 rk_clrsetreg(&cru->clksel_con[1], in rv1126_armclk_set_clk()
584 rk_clrsetreg(&cru->clksel_con[1], in rv1126_armclk_set_clk()
589 priv->cru, APLL, hz)) in rv1126_armclk_set_clk()
598 struct rv1126_cru *cru = priv->cru; in rv1126_pdcore_get_clk() local
601 con = readl(&cru->clksel_con[0]); in rv1126_pdcore_get_clk()
609 struct rv1126_cru *cru = priv->cru; in rv1126_pdcore_set_clk() local
614 rk_clrsetreg(&cru->clksel_con[0], CORE_HCLK_DIV_MASK, in rv1126_pdcore_set_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drv1106.dtsi5 #include <dt-bindings/clock/rv1106-cru.h>
252 compatible = "rockchip,rv1106-grf-cru";
297 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
299 assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
328 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
351 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
353 resets = <&cru SRST_M_DSM>;
369 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
380 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
[all …]
H A Drv1126.dtsi6 #include <dt-bindings/clock/rv1126-cru.h>
53 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
73 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
573 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
575 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
594 clocks = <&cru ACLK_NPU>,
595 <&cru HCLK_NPU>,
596 <&cru PCLK_PDNPU>,
[all …]
H A Drk3588s.dtsi6 #include <dt-bindings/clock/rk3588-cru.h>
245 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
246 <&cru ACLK_USB3OTG0>;
258 resets = <&cru SRST_A_USB3OTG0>;
278 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
290 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
302 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
314 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
348 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
349 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>;
[all …]
H A Drk3568.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
65 clocks = <&cru ARMCLK>;
74 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
92 clocks = <&cru ARMCLK>;
212 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
213 <&cru CLK_SATA0_RXOOB>;
227 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
228 <&cru CLK_SATA1_RXOOB>;
242 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
[all …]
H A Drk3588.dtsi21 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
22 <&cru ACLK_USB3OTG1>;
34 resets = <&cru SRST_A_USB3OTG1>;
74 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
76 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
100 clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>;
109 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
113 resets = <&cru SRST_M_I2S8_8CH_TX>;
126 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
135 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
[all …]
H A Drv1103b.dtsi6 #include <dt-bindings/clock/rockchip,rv1103b-cru.h>
86 clocks = <&cru ARMCLK>;
236 cru: clock-controller@20000000 { label
237 compatible = "rockchip,rv1103b-cru";
243 <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>;
301 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
316 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
330 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
342 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
354 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
[all …]
H A Drk3528.dtsi6 #include <dt-bindings/clock/rk3528-cru.h>
359 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
360 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
361 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
362 <&cru PCLK_PCIE_PHY>;
396 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
397 <&cru SRST_PRESETN_CRU_PCIE>;
412 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
413 <&cru ACLK_USB3OTG>;
429 resets = <&cru SRST_ARESETN_USB3OTG>;
[all …]
H A Drk3576.dtsi6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
143 clocks = <&cru CLK_SAI0_MCLKOUT>;
153 clocks = <&cru CLK_SAI1_MCLKOUT>;
163 clocks = <&cru CLK_SAI2_MCLKOUT>;
173 clocks = <&cru CLK_SAI3_MCLKOUT>;
183 clocks = <&cru CLK_SAI4_MCLKOUT>;
193 clocks = <&cru CLK_SAI4_MCLKOUT>;
246 clocks = <&cru ACLK_VOP_ROOT>;
264 clocks = <&cru HCLK_VOP_ROOT>;
273 clocks = <&cru ACLK_VOP_ROOT>;
[all …]
H A Drk3562.dtsi6 #include <dt-bindings/clock/rk3562-cru.h>
87 clocks = <&cru ACLK_ISP>;
96 clocks = <&cru ACLK_TOP_VIO>;
105 clocks = <&cru ACLK_TOP_VIO>;
114 clocks = <&cru ACLK_TOP_VIO>;
123 clocks = <&cru ACLK_VOP>;
138 clocks = <&cru ARMCLK>;
146 clocks = <&cru ARMCLK>;
154 clocks = <&cru ARMCLK>;
162 clocks = <&cru ARMCLK>;
[all …]

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