Lines Matching refs:cru
6 #include <dt-bindings/clock/rockchip,rv1103b-cru.h>
86 clocks = <&cru ARMCLK>;
236 cru: clock-controller@20000000 { label
237 compatible = "rockchip,rv1103b-cru";
243 <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>;
301 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
316 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
330 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
342 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
354 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
366 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
375 clocks = <&cru PCLK_LPMCU_MAILBOX>;
385 clocks = <&cru PCLK_LPMCU_MAILBOX>;
395 clocks = <&cru PCLK_LPMCU_MAILBOX>;
405 clocks = <&cru PCLK_LPMCU_MAILBOX>;
416 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>;
425 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>;
438 clocks = <&cru MCLK_SAI>, <&cru HCLK_SAI>;
442 resets = <&cru SRST_MRESETN_SAI>, <&cru SRST_HRESETN_SAI>;
453 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
454 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
456 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
458 resets = <&cru SRST_RESETN_CORE_CRYPTO>;
467 clocks = <&cru HCLK_RK_RNG_NS>;
469 resets = <&cru SRST_HRESETN_RK_RNG_NS>;
486 clocks = <&cru ACLK_RKDMA>;
496 clocks = <&cru PCLK_RTC_ROOT>;
498 assigned-clocks = <&cru PCLK_RTC_ROOT>;
510 clocks = <&cru ACLK_MAC>, <&cru PCLK_MAC>;
512 resets = <&cru SRST_ARESETN_MAC>;
543 clocks = <&cru CLK_MACPHY>;
544 resets = <&cru SRST_RESETN_MACPHY>;
580 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
581 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>,
582 <&cru CLK_OTPC_ARB>;
584 resets = <&cru SRST_RESETN_USER_OTPC_NS>, <&cru SRST_RESETN_SBPI_OTPC_NS>,
585 <&cru SRST_PRESETN_OTPC_NS>, <&cru SRST_PRESETN_OTP_MASK>,
586 <&cru SRST_RESETN_OTPC_ARB>;
620 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
637 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
652 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
662 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
674 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
687 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
700 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
713 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
727 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
739 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
751 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
763 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
775 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
787 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
799 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
811 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
821 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
823 resets = <&cru SRST_PRESETN_SARADC>;
832 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>;
834 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
836 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>;
850 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
852 resets = <&cru SRST_DRESETN_DECOM>;
861 clocks = <&cru PCLK_HPMCU_MAILBOX>;
871 clocks = <&cru PCLK_HPMCU_MAILBOX>;
881 clocks = <&cru PCLK_HPMCU_MAILBOX>;
891 clocks = <&cru PCLK_HPMCU_MAILBOX>;
899 clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>,
900 <&cru ACLK_USBOTG>;
911 resets = <&cru SRST_ARESETN_USBOTG>;
937 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
938 <&cru CLK_CORE_ISP>, <&cru ISP0CLK_VICAP>;
950 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
951 <&cru DCLK_VICAP>, <&cru ISP0CLK_VICAP>;
954 resets = <&cru SRST_ARESETN_VICAP>, <&cru SRST_HRESETN_VICAP>,
955 <&cru SRST_DRESETN_VICAP>, <&cru SRST_ISP0RESETN_VICAP>;
966 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>;
980 clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>;
991 clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
1007 clocks = <&cru PCLK_CSI2HOST0>;
1009 resets = <&cru SRST_PRESETN_CSI2HOST0>;
1021 clocks = <&cru PCLK_CSI2HOST1>;
1023 resets = <&cru SRST_PRESETN_CSI2HOST1>;
1031 clocks = <&cru PCLK_CSIPHY>;
1033 resets = <&cru SRST_PRESETN_CSIPHY>;
1042 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
1044 resets = <&cru SRST_RESETN_USBPHY_POR>, <&cru SRST_RESETN_USBPHY_OTG>;
1066 clocks = <&cru PCLK_ACODEC>,
1067 <&cru MCLK_ACODEC_TX>,
1068 <&cru MCLK_SAI>;
1070 resets = <&cru SRST_PRESETN_ACODEC>;
1084 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>;
1087 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
1089 resets = <&cru SRST_ARESETN_VEPU>, <&cru SRST_HRESETN_VEPU>,
1090 <&cru SRST_RESETN_CORE_VEPU>;
1117 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
1129 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1141 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;