arm/dts/rv1106.dtsi

5 #include <dt-bindings/clock/rv1106-cru.h>
252 			compatible = "rockchip,rv1106-grf-cru";
297 		clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
299 		assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
328 		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
341 		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
351 		clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
353 		resets = <&cru SRST_M_DSM>;
369 		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
380 		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
391 		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
404 		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
415 		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
426 		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
437 		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
450 		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
460 		clocks = <&cru PCLK_PMU_MAILBOX>;
471 	cru: clock-controller@ff3a0000 {  label
472 		compatible = "rockchip,rv1106-cru";
479 			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
480 			<&cru ARMCLK>,
481 			<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
482 			<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
483 			<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
484 			<&cru HCLK_PMU_ROOT>;
499 		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
501 		resets = <&cru SRST_P_SARADC>;
511 		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>;
513 		assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
515 		resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
529 		clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
530 			 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>,
531 			 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>;
533 		resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
534 			 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>,
535 			 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>;
567 		clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
569 		resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>;
589 		clocks = <&cru PCLK_MIPICSIPHY>;
591 		resets = <&cru SRST_P_MIPICSIPHY>;
610 		clocks = <&cru ACLK_DMAC>;
619 		clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
620 			 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
622 		assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
624 		resets = <&cru SRST_CORE_CRYPTO>;
633 		clocks = <&cru HCLK_TRNG_NS>;
635 		resets = <&cru SRST_H_TRNG_NS>;
646 		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
659 		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
672 		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
685 		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
696 		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
707 		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
720 		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
733 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
748 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
763 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
778 		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
793 		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
808 		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
821 		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
836 		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
849 		clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
851 		resets = <&cru SRST_D_DECOM>;
864 		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
867 		resets = <&cru SRST_P_WDT_NS>;
877 		clocks = <&cru PCLK_MAILBOX>;
887 		clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
889 		resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>;
898 		clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
909 		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
928 		clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
943 		clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
944 			 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>;
956 		clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
957 			 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
958 			 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
959 			 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
960 			 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>,
961 			 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>;
968 		resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
969 			 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
970 			 <&cru SRST_VICAP_I0>, <&cru SRST_VICAP_I1>,
971 			 <&cru SRST_VICAP_RX0>, <&cru SRST_VICAP_RX1>,
972 			 <&cru SRST_VICAP_ISP0>, <&cru SRST_P_VICAP_VEPU>;
989 		clocks = <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>;
991 		resets = <&cru SRST_P_CSIHOST0>;
1003 		clocks = <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>;
1005 		resets = <&cru SRST_P_CSIHOST1>;
1015 		clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>;
1018 		assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
1020 		resets = <&cru SRST_A_VEPU>, <&cru SRST_H_VEPU>, <&cru SRST_CORE_VEPU>;
1033 		clocks = <&cru CLK_CORE_VEPU_DVBM>;
1035 		assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>;
1037 		resets = <&cru SRST_CORE_VEPU_DVBM>;
1049 		clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>,
1050 			 <&cru ACLK_MAC>, <&cru PCLK_MAC>;
1053 		resets = <&cru SRST_A_MAC>;
1081 				clocks = <&cru CLK_MACPHY>;
1082 				resets = <&cru SRST_MACPHY>;
1114 		clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>,
1127 		clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>,
1143 		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1145 		assigned-clocks = <&cru SCLK_SFC>;
1156 		clocks = <&cru ACLK_IVE>, <&cru HCLK_IVE>;
1165 		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>;
1169 		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1178 		clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>,
1179 			 <&cru ACLK_USBOTG>;
1190 			resets = <&cru SRST_A_USBOTG>;
1218 			clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
1231 			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1244 			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1257 			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1270 			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;