Lines Matching refs:cru
6 #include <dt-bindings/clock/rk3568-cru.h>
65 clocks = <&cru ARMCLK>;
74 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
92 clocks = <&cru ARMCLK>;
212 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
213 <&cru CLK_SATA0_RXOOB>;
227 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
228 <&cru CLK_SATA1_RXOOB>;
242 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
243 <&cru CLK_SATA2_RXOOB>;
256 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
257 <&cru ACLK_USB3OTG0>;
274 resets = <&cru SRST_USB3OTG0>;
288 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
289 <&cru ACLK_USB3OTG1>;
306 resets = <&cru SRST_USB3OTG1>;
341 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
342 <&cru PCLK_USB>, <&usb2phy1>;
353 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
354 <&cru PCLK_USB>, <&usb2phy1>;
365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
366 <&cru PCLK_USB>, <&usb2phy1>;
377 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
378 <&cru PCLK_USB>, <&usb2phy1>;
533 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
535 resets = <&cru SRST_P_EDPPHY_GRF>;
554 cru: clock-controller@fdd20000 { label
555 compatible = "rockchip,rk3568-cru";
563 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
564 <&cru PLL_GPLL>, <&cru ARMCLK>,
565 <&cru ACLK_BUS>, <&cru PCLK_BUS>,
566 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
567 <&cru HCLK_TOP>, <&cru PCLK_TOP>,
568 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
569 <&cru PLL_NPLL>;
668 clocks = <&cru ACLK_NPU_PRE>,
669 <&cru HCLK_NPU_PRE>,
670 <&cru PCLK_NPU_PRE>;
676 clocks = <&cru ACLK_GPU_PRE>,
677 <&cru PCLK_GPU_PRE>;
683 clocks = <&cru HCLK_VI>,
684 <&cru PCLK_VI>;
691 clocks = <&cru HCLK_VO>,
692 <&cru PCLK_VO>,
693 <&cru ACLK_VOP_PRE>;
700 clocks = <&cru HCLK_RGA_PRE>,
701 <&cru PCLK_RGA_PRE>;
711 clocks = <&cru HCLK_VPU_PRE>;
715 clocks = <&cru HCLK_RKVDEC_PRE>;
721 clocks = <&cru HCLK_RKVENC_PRE>;
728 clocks = <&cru PCLK_PIPE>;
748 clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>;
750 resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>;
768 clocks = <&cru CLK_GPU>;
812 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
814 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
827 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>,
828 <&cru HCLK_NPU_PRE>;
830 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
841 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
843 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
859 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
869 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
879 clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
892 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
895 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
911 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
921 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
924 resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
940 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
950 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
952 resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>,
953 <&cru SRST_IEP_CORE>;
968 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
980 clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
990 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
991 <&cru CLK_RKVENC_CORE>;
996 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
997 <&cru SRST_RKVENC_CORE>;
999 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1016 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
1030 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
1031 <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
1032 <&cru CLK_RKVDEC_HEVC_CA>;
1040 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
1041 <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
1042 <&cru SRST_RKVDEC_HEVC_CA>;
1043 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
1044 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
1061 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1075 clocks = <&cru PCLK_CSI2HOST1>, <&cru SRST_P_CSI2HOST1>;
1088 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
1089 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
1092 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
1093 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
1094 <&cru SRST_I_VICAP>;
1098 assigned-clocks = <&cru DCLK_VICAP>;
1111 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
1152 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
1154 resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>;
1167 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1194 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
1195 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
1196 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
1197 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
1202 resets = <&cru SRST_A_GMAC1>;
1242 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
1344 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1354 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&mipi_dphy0>;
1356 resets = <&cru SRST_P_DSITX_0>;
1392 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&mipi_dphy1>;
1394 resets = <&cru SRST_P_DSITX_1>;
1430 clocks = <&cru PCLK_HDMI_HOST>,
1431 <&cru CLK_HDMI_SFR>,
1432 <&cru CLK_HDMI_CEC>,
1434 <&cru HCLK_VOP>;
1469 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
1470 <&cru CLK_EDP_200M>, <&cru HCLK_VO>;
1472 resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>;
1642 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
1643 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
1646 resets = <&cru SRST_SDMMC2>;
1656 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
1657 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>;
1683 resets = <&cru SRST_PCIE20_POWERUP>;
1693 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
1694 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>;
1720 resets = <&cru SRST_PCIE30X1_POWERUP>;
1731 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
1732 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>;
1758 resets = <&cru SRST_PCIE30X2_POWERUP>;
1771 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
1772 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
1773 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
1774 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
1779 resets = <&cru SRST_A_GMAC0>;
1819 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1820 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1823 resets = <&cru SRST_SDMMC0>;
1836 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1837 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1840 resets = <&cru SRST_SDMMC1>;
1849 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1851 assigned-clocks = <&cru SCLK_SFC>;
1861 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1863 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1864 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1865 <&cru TCLK_EMMC>;
1875 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
1883 clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>;
1899 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1903 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1905 rockchip,cru = <&cru>;
1916 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1920 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1922 rockchip,cru = <&cru>;
1945 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1949 rockchip,cru = <&cru>;
1965 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
1969 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1971 rockchip,cru = <&cru>;
1985 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1997 clocks = <&cru HCLK_VAD>;
2014 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
2024 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
2037 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
2038 <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>;
2042 resets = <&cru SRST_ACDCDIG>;
2054 clocks = <&cru ACLK_BUS>;
2065 clocks = <&cru ACLK_BUS>;
2075 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
2077 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
2088 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
2090 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
2101 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
2103 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
2113 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
2126 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
2139 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
2152 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
2165 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
2178 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
2181 resets = <&cru SRST_T_WDT_NS>;
2192 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
2208 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
2224 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
2240 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
2254 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
2268 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
2282 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
2296 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
2310 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
2324 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
2338 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
2352 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
2366 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
2382 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2393 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2404 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2415 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2426 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2437 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2448 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2459 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2470 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2481 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2492 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2503 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2513 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2515 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
2517 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
2518 <&cru SRST_TSADCPHY>;
2535 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2537 resets = <&cru SRST_P_SARADC>;
2550 clocks = <&cru PCLK_MAILBOX>;
2560 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
2564 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
2575 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>;
2579 resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
2590 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>;
2594 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
2604 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
2608 resets = <&cru SRST_P_MIPIDSIPHY0>;
2621 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
2624 resets = <&cru SRST_P_MIPIDSIPHY0>;
2634 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
2638 resets = <&cru SRST_P_MIPIDSIPHY1>;
2651 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
2654 resets = <&cru SRST_P_MIPIDSIPHY1>;
2664 clocks = <&cru PCLK_MIPICSIPHY>;
2677 assigned-clocks = <&cru USB480M>;
2720 <&cru PCLK_PCIE30PHY>;
2722 resets = <&cru SRST_PCIE30PHY>;
2753 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2766 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2779 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2792 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;