Lines Matching refs:cru
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
143 clocks = <&cru CLK_SAI0_MCLKOUT>;
153 clocks = <&cru CLK_SAI1_MCLKOUT>;
163 clocks = <&cru CLK_SAI2_MCLKOUT>;
173 clocks = <&cru CLK_SAI3_MCLKOUT>;
183 clocks = <&cru CLK_SAI4_MCLKOUT>;
193 clocks = <&cru CLK_SAI4_MCLKOUT>;
246 clocks = <&cru ACLK_VOP_ROOT>;
264 clocks = <&cru HCLK_VOP_ROOT>;
273 clocks = <&cru ACLK_VOP_ROOT>;
282 clocks = <&cru ACLK_VOP_ROOT>;
291 clocks = <&cru ACLK_NVM_ROOT>;
309 clocks = <&cru ACLK_VPU_ROOT>;
318 clocks = <&cru ACLK_VPU_ROOT>;
327 clocks = <&cru ACLK_VPU_ROOT>;
336 clocks = <&cru ACLK_VI_ROOT>;
345 clocks = <&cru HCLK_VOP_ROOT>;
354 clocks = <&cru HCLK_VOP_ROOT>;
363 clocks = <&cru HCLK_NVM_ROOT>;
381 clocks = <&cru HCLK_VI_ROOT>;
428 clocks = <&cru ARMCLK_L>;
438 clocks = <&cru ARMCLK_L>;
448 clocks = <&cru ARMCLK_L>;
458 clocks = <&cru ARMCLK_L>;
468 clocks = <&cru ARMCLK_B>;
478 clocks = <&cru ARMCLK_B>;
488 clocks = <&cru ARMCLK_B>;
498 clocks = <&cru ARMCLK_B>;
1230 clocks = <&cru CLK_REF_USB3OTG0>,
1231 <&cru CLK_SUSPEND_USB3OTG0>,
1232 <&cru ACLK_USB3OTG0>;
1236 resets = <&cru SRST_A_USB3OTG0>;
1256 clocks = <&cru CLK_REF_USB3OTG1>,
1257 <&cru CLK_SUSPEND_USB3OTG1>,
1258 <&cru ACLK_USB3OTG1>;
1262 resets = <&cru SRST_A_USB3OTG1>;
1288 clocks = <&cru PCLK_VO0_ROOT>;
1294 clocks = <&cru PCLK_USB_ROOT>;
1300 clocks = <&cru PCLK_PHP_ROOT>;
1328 clocks = <&cru PCLK_PCIE2_COMBOPHY0>;
1334 clocks = <&cru PCLK_PCIE2_COMBOPHY1>;
1340 clocks = <&cru PCLK_PMUPHY_ROOT>;
1348 clocks = <&cru PCLK_PMUPHY_ROOT>;
1353 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
1355 clocks = <&cru CLK_PHY_REF_SRC>;
1375 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
1377 clocks = <&cru CLK_PHY_REF_SRC>;
1398 clocks = <&cru PCLK_PMUPHY_ROOT>;
1404 clocks = <&cru PCLK_PMUPHY_ROOT>;
1410 clocks = <&cru PCLK_VO1_ROOT>;
1416 clocks = <&cru PCLK_SDGMAC_ROOT>;
1422 clocks = <&cru PCLK_PMUPHY_ROOT>;
1470 cru: clock-controller@27200000 { label
1471 compatible = "rockchip,rk3576-cru";
1478 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1479 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
1480 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>;
1490 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
1495 resets = <&cru SRST_I2C0>, <&cru SRST_P_I2C0>;
1506 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1523 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
1535 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
1636 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>, <&cru CLK_PDM0_OUT>;
1659 clocks = <&cru ACLK_RKNN0>, <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>,
1660 <&cru ACLK_RKNN_CBUF>, <&cru HCLK_RKNN_CBUF>;
1663 resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>,
1664 <&cru SRST_A_RKNN_CBUF>, <&cru SRST_A_RKNN_CBUF>;
1682 clocks = <&cru ACLK_RKNN0>, <&cru ACLK_RKNN1>, <&cru HCLK_RKNN_ROOT>;
1700 clocks = <&cru CLK_GPU>;
1734 clocks = <&cru HCLK_EBC>, <&cru ACLK_EBC>, <&cru DCLK_EBC>;
1748 clocks = <&cru ACLK_EBC>, <&cru DCLK_EBC>, <&cru HCLK_EBC>;
1786 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>;
1791 resets = <&cru SRST_A_JPEG>, <&cru SRST_H_JPEG>;
1807 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>;
1812 resets = <&cru SRST_A_JPEG>, <&cru SRST_H_JPEG>;
1828 clocks = <&aclk_jpeg>, <&cru HCLK_JPEG>;
1841 clocks = <&cru ACLK_RGA2E_0>, <&cru HCLK_RGA2E_0>, <&cru CLK_CORE_RGA2E_0>;
1853 clocks = <&cru ACLK_RGA2E_0>, <&cru HCLK_RGA2E_0>;
1865 clocks = <&cru ACLK_RGA2E_1>, <&cru HCLK_RGA2E_1>, <&cru CLK_CORE_RGA2E_1>;
1877 clocks = <&cru ACLK_RGA2E_1>, <&cru HCLK_RGA2E_1>;
1889 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1892 assigned-clocks = <&aclk_vdpp>, <&cru CLK_CORE_VDPP>;
1894 resets = <&cru SRST_A_VDPP>, <&cru SRST_H_VDPP>, <&cru SRST_CORE_VDPP>;
1909 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>;
1923 clocks = <&aclk_vdpp>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1926 assigned-clocks = <&aclk_vdpp>, <&cru CLK_CORE_VDPP>;
1928 resets = <&cru SRST_A_VDPP>, <&cru SRST_H_VDPP>, <&cru SRST_CORE_VDPP>;
1944 clocks = <&aclk_vepu0>, <&hclk_vepu0>, <&cru CLK_VEPU0_CORE>;
1947 resets = <&cru SRST_A_VEPU0>, <&cru SRST_H_VEPU0>,
1948 <&cru SRST_VEPU0_CORE>;
1950 assigned-clocks = <&aclk_vepu0>, <&cru CLK_VEPU0_CORE>;
1981 clocks = <&cru ACLK_VEPU1>, <&cru HCLK_VEPU1>, <&cru CLK_VEPU1_CORE>;
1984 resets = <&cru SRST_A_VEPU1>, <&cru SRST_H_VEPU1>,
1985 <&cru SRST_VEPU1_CORE>;
1987 assigned-clocks = <&cru ACLK_VEPU1>, <&cru CLK_VEPU1_CORE>;
2003 clocks = <&cru ACLK_VEPU1>, <&cru HCLK_VEPU1>;
2019 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC_ROOT>,
2020 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
2022 resets = <&cru SRST_A_RKVDEC_BIU >, <&cru SRST_H_RKVDEC_BIU>,
2023 <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>;
2026 assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC_ROOT>,
2027 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
2042 clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>;
2059 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
2060 <&cru CLK_ISP_CORE>, <&cru CLK_ISP_CORE_MARVIN>,
2061 <&cru CLK_ISP_CORE_VICAP>;
2075 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
2089 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>,
2090 <&cru CLK_VICAP_I0CLK>, <&cru CLK_VICAP_I1CLK>,
2091 <&cru CLK_VICAP_I2CLK>, <&cru CLK_VICAP_I3CLK>,
2092 <&cru CLK_VICAP_I4CLK>;
2097 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>,
2098 <&cru SRST_VICAP_I0CLK>, <&cru SRST_VICAP_I1CLK>,
2099 <&cru SRST_VICAP_I2CLK>, <&cru SRST_VICAP_I3CLK>,
2100 <&cru SRST_VICAP_I4CLK>;
2104 assigned-clocks = <&cru DCLK_VICAP>;
2117 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
2131 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>,
2132 <&cru CLK_CORE_VPSS>;
2144 clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>;
2159 clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>;
2161 resets = <&cru SRST_P_CSI_HOST_0>;
2173 clocks = <&cru PCLK_CSI_HOST_1>;
2175 resets = <&cru SRST_P_CSI_HOST_1>;
2187 clocks = <&cru PCLK_CSI_HOST_2>;
2189 resets = <&cru SRST_P_CSI_HOST_2>;
2201 clocks = <&cru PCLK_CSI_HOST_3>;
2203 resets = <&cru SRST_P_CSI_HOST_3>;
2215 clocks = <&cru PCLK_CSI_HOST_4>;
2217 resets = <&cru SRST_P_CSI_HOST_4>;
2240 clocks = <&cru ACLK_VOP>,
2241 <&cru HCLK_VOP>,
2242 <&cru DCLK_VP0_SRC>,
2243 <&cru DCLK_VP1_SRC>,
2244 <&cru DCLK_VP2_SRC>;
2386 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
2398 clocks = <&cru MCLK_SPDIF_TX2>, <&cru HCLK_SPDIF_TX2>;
2411 clocks = <&cru MCLK_SPDIF_RX2>, <&cru HCLK_SPDIF_RX2>;
2416 resets = <&cru SRST_M_SPDIF_RX2>;
2425 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
2430 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
2441 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
2446 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
2457 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
2459 resets = <&cru SRST_P_DSIHOST0>;
2509 clocks = <&aclk_hdcp0>, <&cru PCLK_HDCP0>,
2510 <&cru HCLK_HDCP0>, <&scmi_clk HCLK_HDCP_KEY0>,
2513 resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>,
2514 <&cru SRST_A_HDCP0>;
2529 clocks = <&cru PCLK_HDMITX0>,
2530 <&cru CLK_HDMITXHPD>,
2531 <&cru CLK_HDMITX0_EARC>,
2532 <&cru CLK_HDMITX0_REF>,
2533 <&cru MCLK_SAI5_8CH>,
2534 <&cru DCLK_VP0>,
2535 <&cru DCLK_VP1>,
2536 <&cru DCLK_VP2>,
2537 <&cru DCLK_EBC>,
2551 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHPD>;
2604 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
2605 <&cru CLK_EDP0_200M>, <&hclk_vo0>;
2607 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
2655 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>,
2656 <&cru ACLK_DP0>;
2658 assigned-clocks = <&cru CLK_AUX16MHZ_0>;
2660 resets = <&cru SRST_DP0>;
2762 clocks = <&aclk_hdcp1>, <&cru PCLK_HDCP1>,
2763 <&cru HCLK_HDCP1>, <&scmi_clk HCLK_HDCP_KEY1>,
2766 resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>,
2767 <&cru SRST_A_HDCP1>;
2778 clocks = <&cru MCLK_SPDIF_TX3>, <&cru HCLK_SPDIF_TX3>;
2791 clocks = <&cru MCLK_SPDIF_TX4>, <&cru HCLK_SPDIF_TX4>;
2804 clocks = <&cru MCLK_SPDIF_TX5>, <&cru HCLK_SPDIF_TX5>;
2817 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>;
2822 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>;
2833 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>;
2838 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>;
2849 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>;
2854 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>;
2866 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
2867 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
2868 <&cru CLK_PCIE0_AUX>;
2903 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
2922 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
2923 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
2924 <&cru CLK_PCIE1_AUX>;
2959 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
2981 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
2982 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
2983 <&cru CLK_GMAC0_PTP_REF>;
2987 resets = <&cru SRST_A_GMAC0>;
3030 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>,
3031 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
3032 <&cru CLK_GMAC1_PTP_REF>;
3036 resets = <&cru SRST_A_GMAC1>;
3074 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
3075 <&cru CLK_RXOOB0>;
3089 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
3090 <&cru CLK_RXOOB1>;
3106 clocks = <&cru ACLK_MMU0>, <&cru ACLK_SLV_MMU0>, <&cru PCLK_PHP_ROOT>;
3118 clocks = <&cru ACLK_MMU1>, <&cru ACLK_SLV_MMU1>, <&cru PCLK_PHP_ROOT>;
3130 clocks = <&cru ACLK_MMU2>, <&cru ACLK_SLV_MMU2>, <&cru PCLK_USB_ROOT>;
3145 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
3146 <&cru CLK_REF_UFS_CLKOUT>;
3149 assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
3150 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
3155 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
3164 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
3166 assigned-clocks = <&cru SCLK_FSPI1_X2>;
3180 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
3183 resets = <&cru SRST_H_SDMMC0>;
3195 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>;
3200 resets = <&cru SRST_H_SDIO>;
3210 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
3212 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
3213 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
3214 <&cru TCLK_EMMC>;
3216 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
3217 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
3218 <&cru SRST_T_EMMC>;
3228 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
3230 assigned-clocks = <&cru SCLK_FSPI_X2>;
3242 clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
3243 <&cru CLK_PKA_CRYPTO_NS>;
3245 assigned-clocks = <&cru ACLK_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>;
3247 resets = <&cru SRST_H_CRYPTO_NS>;
3256 clocks = <&cru HCLK_TRNG_NS>;
3258 resets = <&cru SRST_H_TRNG_NS>;
3268 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>;
3270 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
3305 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
3310 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
3332 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
3337 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
3356 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
3361 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
3377 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
3382 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
3398 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
3403 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
3419 clocks = <&cru MCLK_SPDIF_RX0>, <&cru HCLK_SPDIF_RX0>;
3424 resets = <&cru SRST_M_SPDIF_RX0>;
3435 clocks = <&cru MCLK_SPDIF_RX1>, <&cru HCLK_SPDIF_RX1>;
3440 resets = <&cru SRST_M_SPDIF_RX1>;
3451 clocks = <&cru MCLK_SPDIF_TX0>, <&cru HCLK_SPDIF_TX0>;
3466 clocks = <&cru MCLK_SPDIF_TX1>, <&cru HCLK_SPDIF_TX1>;
3480 clocks = <&cru MCLK_ACDCDIG_DSM>, <&cru HCLK_ACDCDIG_DSM>;
3482 resets = <&cru SRST_M_ACDCDIG_DSM>;
3499 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>, <&cru CLK_PDM1_OUT>;
3501 assigned-clocks = <&cru MCLK_PDM1>;
3502 assigned-clock-parents = <&cru PLL_AUPLL>;
3545 clocks = <&cru ACLK_DMAC0>;
3556 clocks = <&cru ACLK_DMAC1>;
3567 clocks = <&cru ACLK_DMAC2>;
3579 clocks = <&cru HCLK_I3C0>, <&cru CLK_I3C0>;
3594 clocks = <&cru HCLK_I3C1>, <&cru CLK_I3C1>;
3607 clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>;
3609 resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>;
3620 clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>;
3622 resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>;
3633 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
3635 resets = <&cru SRST_D_DECOM>;
3643 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
3648 resets = <&cru SRST_I2C1>, <&cru SRST_P_I2C1>;
3658 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
3663 resets = <&cru SRST_I2C2>, <&cru SRST_P_I2C2>;
3673 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
3678 resets = <&cru SRST_I2C3>, <&cru SRST_P_I2C3>;
3688 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
3693 resets = <&cru SRST_I2C4>, <&cru SRST_P_I2C4>;
3703 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
3708 resets = <&cru SRST_I2C5>, <&cru SRST_P_I2C5>;
3719 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
3724 resets = <&cru SRST_I2C6>, <&cru SRST_P_I2C6>;
3734 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
3739 resets = <&cru SRST_I2C7>, <&cru SRST_P_I2C7>;
3749 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
3754 resets = <&cru SRST_I2C8>, <&cru SRST_P_I2C8>;
3765 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>;
3772 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
3784 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
3800 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
3816 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
3832 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
3848 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
3862 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
3876 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
3890 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
3904 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
3918 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
3932 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
3946 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
3960 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
3974 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
3991 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
4003 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
4015 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
4027 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
4039 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
4051 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
4063 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4075 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4087 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4099 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4111 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4123 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4135 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4147 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
4157 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
4159 resets = <&cru SRST_P_SARADC>;
4168 clocks = <&cru PCLK_MAILBOX0>;
4178 clocks = <&cru PCLK_MAILBOX0>;
4188 clocks = <&cru PCLK_MAILBOX0>;
4198 clocks = <&cru PCLK_MAILBOX0>;
4208 clocks = <&cru PCLK_MAILBOX0>;
4218 clocks = <&cru PCLK_MAILBOX0>;
4228 clocks = <&cru PCLK_MAILBOX0>;
4238 clocks = <&cru PCLK_MAILBOX0>;
4248 clocks = <&cru PCLK_MAILBOX0>;
4258 clocks = <&cru PCLK_MAILBOX0>;
4268 clocks = <&cru PCLK_MAILBOX0>;
4278 clocks = <&cru PCLK_MAILBOX0>;
4288 clocks = <&cru PCLK_MAILBOX0>;
4298 clocks = <&cru PCLK_MAILBOX0>;
4308 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
4310 assigned-clocks = <&cru CLK_TSADC>;
4312 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
4324 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>;
4329 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>;
4340 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>;
4354 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>;
4367 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_PMUPHY_ROOT>;
4369 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
4370 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
4380 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_PMUPHY_ROOT>;
4384 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
4385 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
4399 clocks = <&cru CLK_PHY_REF_SRC >,
4400 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
4401 <&cru PCLK_USBDPPHY>;
4403 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
4404 <&cru SRST_USBDP_COMBO_PHY_CMN>,
4405 <&cru SRST_USBDP_COMBO_PHY_LANE>,
4406 <&cru SRST_USBDP_COMBO_PHY_PCS>,
4407 <&cru SRST_P_USBDPPHY>;
4426 clocks = <&cru PCLK_MIPI_DCPHY>;
4428 resets = <&cru SRST_M_MIPI_DCPHY>,
4429 <&cru SRST_P_MIPI_DCPHY>,
4430 <&cru SRST_P_DCPHY_GRF>,
4431 <&cru SRST_S_MIPI_DCPHY>;
4440 clocks = <&cru PCLK_CSIDPHY>;
4442 resets = <&cru SRST_P_CSIPHY>;
4453 clocks = <&cru CLK_REF_PCIE0_PHY>,
4454 <&cru PCLK_PCIE2_COMBOPHY0>,
4455 <&cru PCLK_PCIE0>;
4457 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
4459 resets = <&cru SRST_P_PCIE2_COMBOPHY0>,
4460 <&cru SRST_PCIE0_PIPE_PHY>;
4471 clocks = <&cru CLK_REF_PCIE1_PHY>,
4472 <&cru PCLK_PCIE2_COMBOPHY1>,
4473 <&cru PCLK_PCIE1>;
4475 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
4477 resets = <&cru SRST_P_PCIE2_COMBOPHY1>,
4478 <&cru SRST_PCIE1_PIPE_PHY>;
4488 clocks = <&cru PCLK_CSIDPHY1>;
4490 resets = <&cru SRST_P_CSIDPHY1>;
4513 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
4526 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
4539 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
4552 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
4565 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;