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/rk3399_ARM-atf/plat/nvidia/tegra/include/t194/
H A Dtegra_def.h15 #define BL31_SIZE U(0x40000)
20 #define PLATFORM_CLUSTER_COUNT U(4)
21 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
34 #define PSTATE_ID_CORE_IDLE U(6)
35 #define PSTATE_ID_CORE_POWERDN U(7)
36 #define PSTATE_ID_SOC_POWERDN U(2)
44 #define PLAT_MAX_RET_STATE U(1)
45 #define PLAT_MAX_OFF_STATE U(8)
50 #define TEGRA194_MAX_SEC_IRQS U(2)
51 #define TEGRA194_TOP_WDT_IRQ U(49)
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/include/t186/
H A Dtegra_def.h16 #define BL31_SIZE U(0x40000)
28 #define MCE_ARI_APERTURE_0_OFFSET U(0x0)
29 #define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
30 #define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
31 #define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
32 #define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
33 #define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
37 #define MCE_ARI_APERTURES_MAX U(6)
40 #define MCE_ARI_APERTURE_SIZE U(0x10000)
45 #define MCE_CORE_ID_MAX U(8)
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/rk3399_ARM-atf/plat/nvidia/tegra/include/t210/
H A Dtegra_def.h16 #define BL31_SIZE U(0x40000)
21 #define PSTATE_ID_CORE_POWERDN U(7)
22 #define PSTATE_ID_CLUSTER_IDLE U(16)
23 #define PSTATE_ID_SOC_POWERDN U(27)
37 #define PLAT_MAX_RET_STATE U(1)
38 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
49 #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400)
59 #define TEGRA_IRAM_BASE U(0x40000000)
60 #define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */
61 #define TEGRA_IRAM_SIZE U(40000) /* 256KB */
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/include/
H A Dt194_nvg.h24 TEGRA_NVG_VERSION_MAJOR = U(6),
25 TEGRA_NVG_VERSION_MINOR = U(7)
29 TEGRA_NVG_CHANNEL_VERSION = U(0),
30 TEGRA_NVG_CHANNEL_POWER_PERF = U(1),
31 TEGRA_NVG_CHANNEL_POWER_MODES = U(2),
32 TEGRA_NVG_CHANNEL_WAKE_TIME = U(3),
33 TEGRA_NVG_CHANNEL_CSTATE_INFO = U(4),
34 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = U(5),
35 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = U(6),
36 TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = U(8),
[all …]
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp_risab_regs.h10 #define RISAB_CR U(0x00)
11 #define RISAB_IASR U(0x08)
12 #define RISAB_IACR U(0x0C)
13 #define RISAB_RIFLOCKR U(0x10)
14 #define RISAB_IAESR U(0x20)
15 #define RISAB_IADDR U(0x24)
16 #define RISAB_PG0_SECCFGR U(0x100)
17 #define RISAB_PG1_SECCFGR U(0x104)
18 #define RISAB_PG2_SECCFGR U(0x108)
19 #define RISAB_PG3_SECCFGR U(0x10C)
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/rk3399_ARM-atf/plat/nxp/soc-ls1046a/ls1046ardb/
H A Dddr_init.c20 .cs[0].config = U(0x80040322),
21 .cs[0].bnds = U(0x1FF),
22 .cs[1].config = U(0x80000322),
23 .cs[1].bnds = U(0x1FF),
24 .sdram_cfg[0] = U(0xE5004000),
25 .sdram_cfg[1] = U(0x401151),
26 .timing_cfg[0] = U(0xD1770018),
27 .timing_cfg[1] = U(0xF2FC9245),
28 .timing_cfg[2] = U(0x594197),
29 .timing_cfg[3] = U(0x2101100),
[all …]
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/lx2160aqds/
H A Dddr_init.c27 .cs[0].bnds = U(0x03FF),
28 .cs[1].bnds = U(0x03FF),
29 .cs[0].config = U(0x80050422),
30 .cs[1].config = U(0x80000422),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
[all …]
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/lx2162aqds/
H A Dddr_init.c27 .cs[0].bnds = U(0x03FFU),
28 .cs[1].bnds = U(0x03FF),
29 .cs[0].config = U(0x80050422),
30 .cs[1].config = U(0x80000422),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
[all …]
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dstm32mp2_def.h54 #define STM32MP2_CHIP_ID U(0x505)
56 #define STM32MP251A_PART_NB U(0x400B3E6D)
57 #define STM32MP251C_PART_NB U(0x000B306D)
58 #define STM32MP251D_PART_NB U(0xC00B3E6D)
59 #define STM32MP251F_PART_NB U(0x800B306D)
60 #define STM32MP253A_PART_NB U(0x400B3E0C)
61 #define STM32MP253C_PART_NB U(0x000B300C)
62 #define STM32MP253D_PART_NB U(0xC00B3E0C)
63 #define STM32MP253F_PART_NB U(0x800B300C)
64 #define STM32MP255A_PART_NB U(0x40082E00)
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/include/
H A Dplatform_def.h18 #define PLAT_PRIMARY_CPU U(0x0)
19 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
20 #define PLATFORM_CLUSTER_COUNT U(1)
21 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
22 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
29 #define PWR_DOMAIN_AT_MAX_LVL U(1)
30 #define PLAT_MAX_PWR_LVL U(2)
31 #define PLAT_MAX_OFF_STATE U(4)
32 #define PLAT_MAX_RET_STATE U(2)
34 #define PLAT_WAIT_RET_STATE U(1)
[all …]
/rk3399_ARM-atf/include/drivers/arm/
H A Dtzc380.h13 #define TZC380_CONFIGURATION_OFF U(0x000)
14 #define ACTION_OFF U(0x004)
15 #define LOCKDOWN_RANGE_OFF U(0x008)
16 #define LOCKDOWN_SELECT_OFF U(0x00C)
17 #define INT_STATUS U(0x010)
18 #define INT_CLEAR U(0x014)
20 #define FAIL_ADDRESS_LOW_OFF U(0x020)
21 #define FAIL_ADDRESS_HIGH_OFF U(0x024)
22 #define FAIL_CONTROL_OFF U(0x028)
23 #define FAIL_ID U(0x02c)
[all …]
H A Dgic600ae_fmu.h13 #define GICFMU_ERRFR_LO U(0x000)
14 #define GICFMU_ERRFR_HI U(0x004)
15 #define GICFMU_ERRCTLR_LO U(0x008)
16 #define GICFMU_ERRCTLR_HI U(0x00C)
17 #define GICFMU_ERRSTATUS_LO U(0x010)
18 #define GICFMU_ERRSTATUS_HI U(0x014)
19 #define GICFMU_ERRGSR_LO U(0xE00)
20 #define GICFMU_ERRGSR_HI U(0xE04)
21 #define GICFMU_KEY U(0xEA0)
22 #define GICFMU_PINGCTLR U(0xEA4)
[all …]
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_def.h36 #define STM32MP1_CHIP_ID U(0x501)
38 #define STM32MP135C_PART_NB U(0x05010000)
39 #define STM32MP135A_PART_NB U(0x05010001)
40 #define STM32MP133C_PART_NB U(0x050100C0)
41 #define STM32MP133A_PART_NB U(0x050100C1)
42 #define STM32MP131C_PART_NB U(0x050106C8)
43 #define STM32MP131A_PART_NB U(0x050106C9)
44 #define STM32MP135F_PART_NB U(0x05010800)
45 #define STM32MP135D_PART_NB U(0x05010801)
46 #define STM32MP133F_PART_NB U(0x050108C0)
[all …]
/rk3399_ARM-atf/include/arch/aarch32/
H A Darch.h15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(24)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_VAR_MASK U(0xf)
20 #define MIDR_REV_SHIFT U(0)
21 #define MIDR_REV_BITS U(4)
22 #define MIDR_REV_MASK U(0xf)
23 #define MIDR_PN_MASK U(0xfff)
24 #define MIDR_PN_SHIFT U(4)
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/include/
H A Dplatform_def.h20 #define PLAT_PRIMARY_CPU U(0x0)
21 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
22 #define PLATFORM_CLUSTER_COUNT U(1)
23 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
24 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
31 #define PWR_DOMAIN_AT_MAX_LVL U(1)
32 #define PLAT_MAX_PWR_LVL U(2)
33 #define PLAT_MAX_OFF_STATE U(4)
34 #define PLAT_MAX_RET_STATE U(2)
36 #define PLAT_WAIT_RET_STATE U(1)
[all …]
/rk3399_ARM-atf/include/lib/hob/
H A Defi_types.h23 #define EFI_BOOT_WITH_FULL_CONFIGURATION U(0x00)
24 #define EFI_BOOT_WITH_MINIMAL_CONFIGURATION U(0x01)
25 #define EFI_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES U(0x02)
26 #define EFI_BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS U(0x03)
27 #define EFI_BOOT_WITH_DEFAULT_SETTINGS U(0x04)
28 #define EFI_BOOT_ON_S4_RESUME U(0x05)
29 #define EFI_BOOT_ON_S5_RESUME U(0x06)
30 #define EFI_BOOT_WITH_MFG_MODE_SETTINGS U(0x07)
31 #define EFI_BOOT_ON_S2_RESUME U(0x10)
32 #define EFI_BOOT_ON_S3_RESUME U(0x11)
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/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/se/
H A Dse_private.h15 #define SE0_SECURITY U(0x18)
19 #define SE0_SHA_GSCID_0 U(0x100)
22 #define SE0_SHA_CONFIG U(0x104)
23 #define SE0_SHA_TASK_CONFIG U(0x108)
24 #define SE0_SHA_CONFIG_HW_INIT_HASH (((uint32_t)1) << 0U)
25 #define SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE U(0)
27 #define SE0_CONFIG_ENC_ALG_SHIFT U(12)
30 #define SE0_CONFIG_DEC_ALG_SHIFT U(8)
33 #define SE0_CONFIG_DST_SHIFT U(2)
36 #define SHA256_HASH_SIZE_BYTES U(256)
[all …]
/rk3399_ARM-atf/include/export/common/tbbr/
H A Dtbbr_img_def_exp.h15 #define FIP_IMAGE_ID U(0)
18 #define BL2_IMAGE_ID U(1)
21 #define SCP_BL2_IMAGE_ID U(2)
24 #define BL31_IMAGE_ID U(3)
27 #define BL32_IMAGE_ID U(4)
30 #define BL33_IMAGE_ID U(5)
33 #define TRUSTED_BOOT_FW_CERT_ID U(6)
34 #define TRUSTED_KEY_CERT_ID U(7)
36 #define SCP_FW_KEY_CERT_ID U(8)
37 #define SOC_FW_KEY_CERT_ID U(9)
[all …]
/rk3399_ARM-atf/plat/renesas/common/include/
H A Drcar_def.h18 #define RCAR_SHARED_MEM_SIZE U(0x00001000)
19 #define FLASH0_BASE U(0x08000000)
20 #define FLASH0_SIZE U(0x04000000)
21 #define FLASH_MEMORY_SIZE U(0x04000000) /* hyper flash */
22 #define FLASH_TRANS_SIZE_UNIT U(0x00000100)
23 #define DEVICE_RCAR_BASE U(0xE6000000)
24 #define DEVICE_RCAR_SIZE U(0x00300000)
25 #define DEVICE_RCAR_BASE2 U(0xE6360000)
26 #define DEVICE_RCAR_SIZE2 U(0x19CA0000)
27 #define DEVICE_SRAM_BASE U(0xE6300000)
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/include/
H A Dplatform_def.h16 #define PLAT_PRIMARY_CPU U(0x0)
17 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
18 #define PLATFORM_CLUSTER_COUNT U(1)
19 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
20 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
27 #define PWR_DOMAIN_AT_MAX_LVL U(1)
28 #define PLAT_MAX_PWR_LVL U(2)
29 #define PLAT_MAX_OFF_STATE U(4)
30 #define PLAT_MAX_RET_STATE U(1)
33 #define PLAT_WAIT_OFF_STATE U(2)
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/include/
H A Dplatform_def.h19 #define PLAT_PRIMARY_CPU U(0x0)
20 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
21 #define PLATFORM_CLUSTER_COUNT U(1)
22 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
23 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
30 #define PWR_DOMAIN_AT_MAX_LVL U(1)
31 #define PLAT_MAX_PWR_LVL U(2)
32 #define PLAT_MAX_OFF_STATE U(4)
33 #define PLAT_MAX_RET_STATE U(2)
35 #define PLAT_WAIT_RET_STATE U(1)
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/ls1028ardb/
H A Dddr_init.c16 .cs[0].config = U(0x80040422),
17 .cs[0].bnds = U(0xFF),
18 .sdram_cfg[0] = U(0xE50C0004),
19 .sdram_cfg[1] = U(0x401100),
20 .timing_cfg[0] = U(0x91550018),
21 .timing_cfg[1] = U(0xBAB40C42),
22 .timing_cfg[2] = U(0x48C111),
23 .timing_cfg[3] = U(0x1111000),
24 .timing_cfg[4] = U(0x2),
25 .timing_cfg[5] = U(0x3401400),
[all …]
/rk3399_ARM-atf/include/drivers/nxp/sfp/
H A Dfuse_prov.h14 #define MASK_NONE U(0xFFFFFFFF)
15 #define ERROR_WRITE U(0xA)
16 #define ERROR_ALREADY_BLOWN U(0xB)
19 #define FLAG_POVDD_SHIFT U(0)
20 #define FLAG_SYSCFG_SHIFT U(1)
21 #define FLAG_SRKH_SHIFT U(2)
22 #define FLAG_MC_SHIFT U(3)
23 #define FLAG_DCV0_SHIFT U(4)
24 #define FLAG_DCV1_SHIFT U(5)
25 #define FLAG_DRV0_SHIFT U(6)
[all …]
/rk3399_ARM-atf/drivers/nxp/ifc/nand/
H A Difc.h14 #define NXP_IFC_RUN_TIME_ADDR U(0x1000)
17 #define EXT_CSPR(n) (U(0x000C) + (n * 0xC))
18 #define CSPR(n) (U(0x0010) + (n * 0xC))
19 #define CSOR(n) (U(0x0130) + (n * 0xC))
20 #define EXT_CSOR(n) (U(0x0134) + (n * 0xC))
21 #define IFC_AMASK_CS0 U(0x00A0)
24 #define NCFGR (NXP_IFC_RUN_TIME_ADDR + U(0x0000))
25 #define NAND_FCR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0014))
27 #define ROW0 (NXP_IFC_RUN_TIME_ADDR + U(0x003C))
28 #define ROW1 (NXP_IFC_RUN_TIME_ADDR + U(0x004C))
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/
H A Dpmc.h17 #define PMC_CONFIG U(0x0)
18 #define PMC_IO_DPD_SAMPLE U(0x20)
19 #define PMC_DPD_ENABLE_0 U(0x24)
20 #define PMC_PWRGATE_STATUS U(0x38)
21 #define PMC_PWRGATE_TOGGLE U(0x30)
22 #define PMC_SCRATCH1 U(0x54)
23 #define PMC_CRYPTO_OP_0 U(0xf4)
24 #define PMC_TOGGLE_START U(0x100)
25 #define PMC_SCRATCH31 U(0x118)
26 #define PMC_SCRATCH32 U(0x11C)
[all …]

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