Lines Matching refs:U
36 #define STM32MP1_CHIP_ID U(0x501)
38 #define STM32MP135C_PART_NB U(0x05010000)
39 #define STM32MP135A_PART_NB U(0x05010001)
40 #define STM32MP133C_PART_NB U(0x050100C0)
41 #define STM32MP133A_PART_NB U(0x050100C1)
42 #define STM32MP131C_PART_NB U(0x050106C8)
43 #define STM32MP131A_PART_NB U(0x050106C9)
44 #define STM32MP135F_PART_NB U(0x05010800)
45 #define STM32MP135D_PART_NB U(0x05010801)
46 #define STM32MP133F_PART_NB U(0x050108C0)
47 #define STM32MP133D_PART_NB U(0x050108C1)
48 #define STM32MP131F_PART_NB U(0x05010EC8)
49 #define STM32MP131D_PART_NB U(0x05010EC9)
52 #define STM32MP1_CHIP_ID U(0x500)
54 #define STM32MP157C_PART_NB U(0x05000000)
55 #define STM32MP157A_PART_NB U(0x05000001)
56 #define STM32MP153C_PART_NB U(0x05000024)
57 #define STM32MP153A_PART_NB U(0x05000025)
58 #define STM32MP151C_PART_NB U(0x0500002E)
59 #define STM32MP151A_PART_NB U(0x0500002F)
60 #define STM32MP157F_PART_NB U(0x05000080)
61 #define STM32MP157D_PART_NB U(0x05000081)
62 #define STM32MP153F_PART_NB U(0x050000A4)
63 #define STM32MP153D_PART_NB U(0x050000A5)
64 #define STM32MP151F_PART_NB U(0x050000AE)
65 #define STM32MP151D_PART_NB U(0x050000AF)
68 #define STM32MP1_REV_B U(0x2000)
70 #define STM32MP1_REV_Y U(0x1003)
71 #define STM32MP1_REV_Z U(0x1001)
74 #define STM32MP1_REV_Z U(0x2001)
81 #define PKG_AA_LFBGA448 U(4)
82 #define PKG_AB_LFBGA354 U(3)
83 #define PKG_AC_TFBGA361 U(2)
84 #define PKG_AD_TFBGA257 U(1)
90 #define STM32MP_ROM_BASE U(0x00000000)
91 #define STM32MP_ROM_SIZE U(0x00020000)
92 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
95 #define STM32MP_SYSRAM_BASE U(0x2FFE0000)
96 #define STM32MP_SYSRAM_SIZE U(0x00020000)
97 #define SRAM1_BASE U(0x30000000)
98 #define SRAM1_SIZE U(0x00004000)
99 #define SRAM2_BASE U(0x30004000)
100 #define SRAM2_SIZE U(0x00002000)
101 #define SRAM3_BASE U(0x30006000)
102 #define SRAM3_SIZE U(0x00002000)
104 #define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
107 #define STM32MP_SYSRAM_BASE U(0x2FFC0000)
108 #define STM32MP_SYSRAM_SIZE U(0x00040000)
124 #define STM32MP_DDR_BASE U(0xC0000000)
125 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
139 #define STM32MP_HEADER_RESERVED_SIZE U(0x200)
146 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
148 #define STM32MP_HEADER_SIZE U(0x00000100)
150 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
163 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
167 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
186 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
188 #define STM32MP_BL33_MAX_SIZE U(0x400000)
200 #define STM32MP1_DEVICE1_BASE U(0x40000000)
201 #define STM32MP1_DEVICE1_SIZE U(0x40000000)
203 #define STM32MP1_DEVICE2_BASE U(0x80000000)
204 #define STM32MP1_DEVICE2_SIZE U(0x40000000)
209 #define RCC_BASE U(0x50000000)
214 #define PWR_BASE U(0x50001000)
219 #define GPIOA_BASE U(0x50002000)
220 #define GPIOB_BASE U(0x50003000)
221 #define GPIOC_BASE U(0x50004000)
222 #define GPIOD_BASE U(0x50005000)
223 #define GPIOE_BASE U(0x50006000)
224 #define GPIOF_BASE U(0x50007000)
225 #define GPIOG_BASE U(0x50008000)
226 #define GPIOH_BASE U(0x50009000)
227 #define GPIOI_BASE U(0x5000A000)
229 #define GPIOJ_BASE U(0x5000B000)
230 #define GPIOK_BASE U(0x5000C000)
231 #define GPIOZ_BASE U(0x54004000)
233 #define GPIO_BANK_OFFSET U(0x1000)
243 #define USART1_BASE U(0x4C000000)
244 #define USART2_BASE U(0x4C001000)
247 #define USART1_BASE U(0x5C000000)
248 #define USART2_BASE U(0x4000E000)
250 #define USART3_BASE U(0x4000F000)
251 #define UART4_BASE U(0x40010000)
252 #define UART5_BASE U(0x40011000)
253 #define USART6_BASE U(0x44003000)
254 #define UART7_BASE U(0x40018000)
255 #define UART8_BASE U(0x40019000)
289 #define STM32MP1_ETZPC_BASE U(0x5C007000)
292 #define STM32MP1_ETZPC_TZMA_ROM U(0)
293 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
387 #define STM32MP1_TZC_BASE U(0x5C006000)
400 #define STM32MP_SDMMC1_BASE U(0x58005000)
401 #define STM32MP_SDMMC2_BASE U(0x58007000)
402 #define STM32MP_SDMMC3_BASE U(0x48004000)
462 #define HW2_OTP_IWDG_HW_POS U(3)
463 #define HW2_OTP_IWDG_FZ_STOP_POS U(5)
464 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
476 #define NAND_PAGE_SIZE_2K U(0)
477 #define NAND_PAGE_SIZE_4K U(1)
478 #define NAND_PAGE_SIZE_8K U(2)
483 #define NAND_BLOCK_SIZE_64_PAGES U(0)
484 #define NAND_BLOCK_SIZE_128_PAGES U(1)
485 #define NAND_BLOCK_SIZE_256_PAGES U(2)
490 #define NAND_BLOCK_NB_UNIT U(256)
499 #define NAND_ECC_BIT_NB_UNSET U(0)
500 #define NAND_ECC_BIT_NB_1_BITS U(1)
501 #define NAND_ECC_BIT_NB_4_BITS U(2)
502 #define NAND_ECC_BIT_NB_8_BITS U(3)
503 #define NAND_ECC_ON_DIE U(4)
513 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
514 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
520 #define UID_WORD_NB U(3)
525 #define TAMP_BASE U(0x5C00A000)
526 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
528 #define TAMP_COUNTR U(0x40)
540 #define USB_OTG_BASE U(0x49000000)
545 #define DDRCTRL_BASE U(0x5A003000)
550 #define DDRPHYC_BASE U(0x5A004000)
556 #define MCE_BASE U(0x58001000)
557 #define MCE_KEY_SIZE_IN_BYTES U(16)
563 #define IWDG_MAX_INSTANCE U(2)
564 #define IWDG1_INST U(0)
565 #define IWDG2_INST U(1)
567 #define IWDG1_BASE U(0x5C003000)
568 #define IWDG2_BASE U(0x5A002000)
573 #define BSEC_BASE U(0x5C005000)
575 #define CRYP_BASE U(0x54002000)
578 #define CRYP1_BASE U(0x54001000)
580 #define DBGMCU_BASE U(0x50081000)
582 #define HASH_BASE U(0x54003000)
585 #define HASH1_BASE U(0x54002000)
588 #define I2C3_BASE U(0x4C004000)
589 #define I2C4_BASE U(0x4C005000)
590 #define I2C5_BASE U(0x4C006000)
593 #define I2C4_BASE U(0x5C002000)
594 #define I2C6_BASE U(0x5c009000)
597 #define RNG_BASE U(0x54004000)
600 #define RNG1_BASE U(0x54003000)
602 #define RTC_BASE U(0x5c004000)
604 #define SPI4_BASE U(0x4C002000)
605 #define SPI5_BASE U(0x4C003000)
608 #define SPI6_BASE U(0x5c001000)
610 #define STGEN_BASE U(0x5c008000)
611 #define SYSCFG_BASE U(0x50020000)
616 #define SAES_BASE U(0x54005000)
621 #define PKA_BASE U(0x54006000)
627 #define PLAT_NB_RDEVS U(19)
629 #define PLAT_NB_FIXED_REGUS U(2)
634 #define PLL1_NOMINAL_FREQ_IN_KHZ U(650000) /* 650MHz */