Lines Matching refs:U
16 #define MIDR_IMPL_MASK U(0xff)
17 #define MIDR_IMPL_SHIFT U(0x18)
18 #define MIDR_VAR_SHIFT U(20)
19 #define MIDR_VAR_BITS U(4)
20 #define MIDR_VAR_MASK U(0xf)
21 #define MIDR_REV_SHIFT U(0)
22 #define MIDR_REV_BITS U(4)
23 #define MIDR_REV_MASK U(0xf)
24 #define MIDR_PN_MASK U(0xfff)
25 #define MIDR_PN_SHIFT U(0x4)
36 #define MPIDR_AFFINITY_BITS U(8)
38 #define MPIDR_AFF0_SHIFT U(0)
39 #define MPIDR_AFF1_SHIFT U(8)
40 #define MPIDR_AFF2_SHIFT U(16)
41 #define MPIDR_AFF3_SHIFT U(32)
44 #define MPIDR_AFFLVL_SHIFT U(3)
63 #define MPIDR_MAX_AFFLVL U(2)
78 #define INVALID_MPID U(0xFFFFFFFF)
162 #define CNTCR_OFF U(0x000)
163 #define CNTCV_OFF U(0x008)
164 #define CNTFID_OFF U(0x020)
166 #define CNTCR_EN (U(1) << 0)
167 #define CNTCR_HDBG (U(1) << 1)
174 #define LOUIS_SHIFT U(21)
175 #define LOC_SHIFT U(24)
176 #define CTYPE_SHIFT(n) U(3 * (n - 1))
177 #define CLIDR_FIELD_WIDTH U(3)
180 #define LEVEL_SHIFT U(1)
183 #define DCISW U(0x0)
184 #define DCCISW U(0x1)
188 #define DCCSW U(0x2)
214 #define ID_AA64PFR0_EL0_SHIFT U(0)
215 #define ID_AA64PFR0_EL1_SHIFT U(4)
216 #define ID_AA64PFR0_EL2_SHIFT U(8)
217 #define ID_AA64PFR0_EL3_SHIFT U(12)
219 #define ID_AA64PFR0_AMU_SHIFT U(44)
222 #define ID_AA64PFR0_AMU_V1P1 U(0x2)
230 #define ID_AA64PFR0_GIC_SHIFT U(24)
231 #define ID_AA64PFR0_GIC_WIDTH U(4)
234 #define ID_AA64PFR0_SVE_SHIFT U(32)
236 #define ID_AA64PFR0_SVE_LENGTH U(4)
239 #define ID_AA64PFR0_SEL2_SHIFT U(36)
242 #define ID_AA64PFR0_MPAM_SHIFT U(40)
245 #define ID_AA64PFR0_DIT_SHIFT U(48)
247 #define ID_AA64PFR0_DIT_LENGTH U(4)
250 #define ID_AA64PFR0_CSV2_SHIFT U(56)
252 #define ID_AA64PFR0_CSV2_LENGTH U(4)
256 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
258 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
262 #define ID_AA64PFR0_RAS_SHIFT U(28)
264 #define ID_AA64PFR0_RAS_LENGTH U(4)
272 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0)
277 #define ID_AA64DFR0_TRACEVER_SHIFT U(4)
279 #define ID_AA64DFR0_TRACEVER_LENGTH U(4)
281 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
282 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
283 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
286 #define ID_AA64DFR0_PMUVER_LENGTH U(4)
287 #define ID_AA64DFR0_PMUVER_SHIFT U(8)
288 #define ID_AA64DFR0_PMUVER_MASK U(0xf)
289 #define ID_AA64DFR0_PMUVER_PMUV3 U(1)
290 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9)
291 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
294 #define ID_AA64DFR0_SEBEP_SHIFT U(24)
299 #define ID_AA64DFR0_PMS_SHIFT U(32)
305 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
310 #define ID_AA64DFR0_MTPMU_SHIFT U(48)
316 #define ID_AA64DFR0_BRBE_SHIFT U(52)
321 #define ID_AA64DFR1_EBEP_SHIFT U(48)
325 #define ID_AA64DFR1_BRP_SHIFT U(8)
326 #define ID_AA64DFR1_BRP_WIDTH U(8)
334 #define ID_AA64ISAR0_ATOMIC_SHIFT U(20)
336 #define ID_AA64ISAR0_RNDR_SHIFT U(60)
339 #define ID_AA64ISAR0_AES_SHIFT U(0x4)
341 #define ID_AA64ISAR0_SHA1_SHIFT U(0x8)
343 #define ID_AA64ISAR0_SHA2_SHIFT U(0xc)
349 #define ID_AA64ISAR1_LS64_SHIFT U(60)
356 #define ID_AA64ISAR1_SB_SHIFT U(36)
361 #define ID_AA64ISAR1_GPI_SHIFT U(28)
363 #define ID_AA64ISAR1_GPA_SHIFT U(24)
366 #define ID_AA64ISAR1_API_SHIFT U(8)
368 #define ID_AA64ISAR1_APA_SHIFT U(4)
373 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16)
378 #define ID_AA64ISAR2_GPA3_SHIFT U(8)
381 #define ID_AA64ISAR2_APA3_SHIFT U(12)
384 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28)
387 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32)
392 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0)
398 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
401 #define PARANGE_0000 U(32)
402 #define PARANGE_0001 U(36)
403 #define PARANGE_0010 U(40)
404 #define PARANGE_0011 U(42)
405 #define PARANGE_0100 U(44)
406 #define PARANGE_0101 U(48)
407 #define PARANGE_0110 U(52)
408 #define PARANGE_0111 U(56)
410 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
415 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
421 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
424 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
427 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
432 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
436 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
442 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
445 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
452 #define ID_AA64MMFR2_EL1_IDS_SHIFT U(36)
455 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
458 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
460 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
462 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4)
465 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
468 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
475 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32)
479 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28)
482 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24)
485 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20)
488 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16)
491 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12)
494 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8)
497 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4)
501 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
507 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16)
511 #define ID_AA64MMFR4_EL1_RME_GDI_SHIFT U(28)
513 #define ID_AA64MMFR4_EL1_RME_GDI_LENGTH U(4)
518 #define ID_AA64PFR1_EL1_BT_SHIFT U(0)
522 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
526 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
529 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
530 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
533 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36)
537 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
541 #define ID_AA64PFR1_EL1_THE_SHIFT U(48)
545 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60)
549 #define ID_AA64PFR1_EL1_CE_SHIFT U(20)
558 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
561 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4)
564 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8)
567 #define ID_AA64PFR2_EL1_UINJ_SHIFT U(16)
571 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32)
580 #define MTE_UNIMPLEMENTED U(0)
582 #define MTE_IMPLEMENTED_EL0 U(1)
584 #define MTE_IMPLEMENTED_ELX U(2)
589 #define MTE_IMPLEMENTED_ASY U(3)
594 #define ID_AA64PFR1_EL1_SME_SHIFT U(24)
596 #define ID_AA64PFR1_EL1_SME_WIDTH U(4)
607 #define ID_PFR1_VIRTEXT_SHIFT U(12)
608 #define ID_PFR1_VIRTEXT_MASK U(0xf)
613 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
614 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
615 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
621 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
622 (U(1) << 4) | (U(1) << 3))
624 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
625 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
626 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
663 #define SCTLR_TCF0_SHIFT U(38)
669 #define SCTLR_TCF0_NO_EFFECT U(0)
671 #define SCTLR_TCF0_SYNC U(1)
673 #define SCTLR_TCF0_ASYNC U(2)
678 #define SCTLR_TCF0_SYNCR_ASYNCW U(3)
680 #define SCTLR_TCF_SHIFT U(40)
684 #define SCTLR_TCF_NO_EFFECT U(0)
686 #define SCTLR_TCF_SYNC U(1)
688 #define SCTLR_TCF_ASYNC U(2)
693 #define SCTLR_TCF_SYNCR_ASYNCW U(3)
697 #define SCTLR_DSSBS_SHIFT U(44)
700 #define SCTLR_TWEDEL_SHIFT U(46)
720 #define CPACR_EL1_SMEN_SHIFT U(24)
725 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
727 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
729 #define SCR_NSE_SHIFT U(62)
738 #define SCR_TWEDEL_SHIFT U(30)
744 #define SCR_ENTP2_SHIFT U(41)
751 #define SCR_AMVOFFEN_SHIFT U(35)
761 #define SCR_EEL2_SHIFT U(18)
777 #define SCR_VALID_BIT_MASK U(0x24000002F8F)
790 #define MDCR_SBRBE_SHIFT U(32)
842 #define HSTR_EL2_RESET_VAL U(0x0)
843 #define HSTR_EL2_T_MASK U(0xff)
846 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
847 #define CNTHP_CTL_RESET_VAL U(0x0)
852 #define VTTBR_VMID_SHIFT U(48)
854 #define VTTBR_BADDR_SHIFT U(0)
858 #define HCR_AMVOFFEN_SHIFT U(51)
866 #define HCR_RW_SHIFT U(31)
875 #define ISR_A_SHIFT U(8)
876 #define ISR_I_SHIFT U(7)
877 #define ISR_F_SHIFT U(6)
880 #define CNTHCTL_RESET_VAL U(0x0)
881 #define EVNTEN_BIT (U(1) << 2)
882 #define EL1PCEN_BIT (U(1) << 1)
883 #define EL1PCTEN_BIT (U(1) << 0)
886 #define EL0PTEN_BIT (U(1) << 9)
887 #define EL0VTEN_BIT (U(1) << 8)
888 #define EL0PCTEN_BIT (U(1) << 0)
889 #define EL0VCTEN_BIT (U(1) << 1)
890 #define EVNTEN_BIT (U(1) << 2)
891 #define EVNTDIR_BIT (U(1) << 3)
892 #define EVNTI_SHIFT U(4)
893 #define EVNTI_MASK U(0xf)
896 #define TCPAC_BIT (U(1) << 31)
897 #define TAM_SHIFT U(30)
898 #define TAM_BIT (U(1) << TAM_SHIFT)
899 #define TTA_BIT (U(1) << 20)
900 #define ESM_BIT (U(1) << 12)
901 #define TFP_BIT (U(1) << 10)
902 #define CPTR_EZ_BIT (U(1) << 8)
905 #define EC_BIT (U(1) << 9)
920 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
921 #define CPTR_EL2_TCPAC_BIT (U(1) << 31)
922 #define CPTR_EL2_TAM_SHIFT U(30)
923 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
925 #define CPTR_EL2_SMEN_SHIFT U(24)
926 #define CPTR_EL2_TTA_BIT (U(1) << 20)
928 #define CPTR_EL2_ZEN_SHIFT U(16)
929 #define CPTR_EL2_TSM_BIT (U(1) << 12)
935 #define VTCR_RESET_VAL U(0x0)
936 #define VTCR_EL2_MSA (U(1) << 31)
939 #define DAIF_FIQ_BIT (U(1) << 0)
940 #define DAIF_IRQ_BIT (U(1) << 1)
941 #define DAIF_ABT_BIT (U(1) << 2)
942 #define DAIF_DBG_BIT (U(1) << 3)
943 #define SPSR_V_BIT (U(1) << 28)
944 #define SPSR_C_BIT (U(1) << 29)
945 #define SPSR_Z_BIT (U(1) << 30)
946 #define SPSR_N_BIT (U(1) << 31)
947 #define SPSR_DAIF_SHIFT U(6)
948 #define SPSR_DAIF_MASK U(0xf)
950 #define SPSR_AIF_SHIFT U(6)
951 #define SPSR_AIF_MASK U(0x7)
953 #define SPSR_E_SHIFT U(9)
954 #define SPSR_E_MASK U(0x1)
955 #define SPSR_E_LITTLE U(0x0)
956 #define SPSR_E_BIG U(0x1)
958 #define SPSR_T_SHIFT U(5)
959 #define SPSR_T_MASK U(0x1)
960 #define SPSR_T_ARM U(0x0)
961 #define SPSR_T_THUMB U(0x1)
963 #define SPSR_M_SHIFT U(4)
964 #define SPSR_M_MASK U(0x1)
965 #define SPSR_M_WIDTH U(1)
966 #define SPSR_M_AARCH64 U(0x0)
967 #define SPSR_M_AARCH32 U(0x1)
968 #define SPSR_M_EL1H U(0x5)
969 #define SPSR_M_EL2H U(0x9)
971 #define SPSR_EL_SHIFT U(2)
972 #define SPSR_EL_WIDTH U(2)
974 #define SPSR_BTYPE_SHIFT_AARCH64 U(10)
975 #define SPSR_BTYPE_MASK_AARCH64 U(0x3)
976 #define SPSR_SSBS_SHIFT_AARCH64 U(12)
978 #define SPSR_SSBS_SHIFT_AARCH32 U(23)
1019 #define RMR_EL3_RR_BIT (U(1) << 1)
1020 #define RMR_EL3_AA64_BIT (U(1) << 0)
1025 #define HI_VECTOR_BASE U(0xFFFF0000)
1032 #define TCR_EL1_IPS_SHIFT U(32)
1033 #define TCR_EL2_PS_SHIFT U(16)
1034 #define TCR_EL3_PS_SHIFT U(16)
1040 #define TCR_T0SZ_SHIFT U(0)
1041 #define TCR_T1SZ_SHIFT U(16)
1086 #define TCR_TG0_SHIFT U(14)
1098 #define TCR_TG1_SHIFT U(30)
1107 #define MODE_SP_SHIFT U(0x0)
1108 #define MODE_SP_MASK U(0x1)
1109 #define MODE_SP_EL0 U(0x0)
1110 #define MODE_SP_ELX U(0x1)
1112 #define MODE_RW_SHIFT U(0x4)
1113 #define MODE_RW_MASK U(0x1)
1114 #define MODE_RW_64 U(0x0)
1115 #define MODE_RW_32 U(0x1)
1117 #define MODE_EL_SHIFT U(0x2)
1118 #define MODE_EL_MASK U(0x3)
1119 #define MODE_EL_WIDTH U(0x2)
1120 #define MODE_EL3 U(0x3)
1121 #define MODE_EL2 U(0x2)
1122 #define MODE_EL1 U(0x1)
1123 #define MODE_EL0 U(0x0)
1125 #define MODE32_SHIFT U(0)
1126 #define MODE32_MASK U(0xf)
1127 #define MODE32_usr U(0x0)
1128 #define MODE32_fiq U(0x1)
1129 #define MODE32_irq U(0x2)
1130 #define MODE32_svc U(0x3)
1131 #define MODE32_mon U(0x6)
1132 #define MODE32_abt U(0x7)
1133 #define MODE32_hyp U(0xa)
1134 #define MODE32_und U(0xb)
1135 #define MODE32_sys U(0xf)
1165 #define CTR_CWG_SHIFT U(24)
1166 #define CTR_CWG_MASK U(0xf)
1167 #define CTR_ERG_SHIFT U(20)
1168 #define CTR_ERG_MASK U(0xf)
1169 #define CTR_DMINLINE_SHIFT U(16)
1170 #define CTR_DMINLINE_MASK U(0xf)
1171 #define CTR_L1IP_SHIFT U(14)
1172 #define CTR_L1IP_MASK U(0x3)
1173 #define CTR_IMINLINE_SHIFT U(0)
1174 #define CTR_IMINLINE_MASK U(0xf)
1176 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
1179 #define CNTP_CTL_ENABLE_SHIFT U(0)
1180 #define CNTP_CTL_IMASK_SHIFT U(1)
1181 #define CNTP_CTL_ISTATUS_SHIFT U(2)
1183 #define CNTP_CTL_ENABLE_MASK U(1)
1184 #define CNTP_CTL_IMASK_MASK U(1)
1185 #define CNTP_CTL_ISTATUS_MASK U(1)
1188 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
1189 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
1192 #define ESR_EC_SHIFT U(26)
1193 #define ESR_EC_MASK U(0x3f)
1194 #define ESR_EC_LENGTH U(6)
1195 #define ESR_EC_WIDTH U(6)
1196 #define ESR_ISS_SHIFT U(0)
1197 #define ESR_ISS_LENGTH U(25)
1198 #define ESR_IL_BIT (U(1) << 25)
1199 #define EC_UNKNOWN U(0x0)
1200 #define EC_WFE_WFI U(0x1)
1201 #define EC_AARCH32_CP15_MRC_MCR U(0x3)
1202 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
1203 #define EC_AARCH32_CP14_MRC_MCR U(0x5)
1204 #define EC_AARCH32_CP14_LDC_STC U(0x6)
1205 #define EC_FP_SIMD U(0x7)
1206 #define EC_AARCH32_CP10_MRC U(0x8)
1207 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
1208 #define EC_ILLEGAL U(0xe)
1209 #define EC_AARCH32_SVC U(0x11)
1210 #define EC_AARCH32_HVC U(0x12)
1211 #define EC_AARCH32_SMC U(0x13)
1212 #define EC_AARCH64_SVC U(0x15)
1213 #define EC_AARCH64_HVC U(0x16)
1214 #define EC_AARCH64_SMC U(0x17)
1215 #define EC_AARCH64_SYS U(0x18)
1216 #define EC_IMP_DEF_EL3 U(0x1f)
1217 #define EC_IABORT_LOWER_EL U(0x20)
1218 #define EC_IABORT_CUR_EL U(0x21)
1219 #define EC_PC_ALIGN U(0x22)
1220 #define EC_DABORT_LOWER_EL U(0x24)
1221 #define EC_DABORT_CUR_EL U(0x25)
1222 #define EC_SP_ALIGN U(0x26)
1223 #define EC_AARCH32_FP U(0x28)
1224 #define EC_AARCH64_FP U(0x2c)
1225 #define EC_SERROR U(0x2f)
1226 #define EC_BRK U(0x3c)
1232 #define ESR_ISS_EABORT_EA_BIT U(9)
1237 #define RMR_RESET_REQUEST_SHIFT U(0x1)
1238 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
1245 #define TLBI_ADDR_SHIFT U(12)
1253 #define CNTCTLBASE_CNTFRQ U(0x0)
1254 #define CNTNSAR U(0x4)
1257 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
1258 #define CNTACR_RPCT_SHIFT U(0x0)
1259 #define CNTACR_RVCT_SHIFT U(0x1)
1260 #define CNTACR_RFRQ_SHIFT U(0x2)
1261 #define CNTACR_RVOFF_SHIFT U(0x3)
1262 #define CNTACR_RWVT_SHIFT U(0x4)
1263 #define CNTACR_RWPT_SHIFT U(0x5)
1270 #define CNTPCT_LO U(0x0)
1272 #define CNTBASEN_CNTFRQ U(0x10)
1274 #define CNTP_CVAL_LO U(0x20)
1276 #define CNTP_CTL U(0x2c)
1279 #define PMCR_EL0_RESET_VAL U(0x0)
1280 #define PMCR_EL0_N_SHIFT U(11)
1281 #define PMCR_EL0_N_MASK U(0x1f)
1283 #define PMCR_EL0_LP_BIT (U(1) << 7)
1284 #define PMCR_EL0_LC_BIT (U(1) << 6)
1285 #define PMCR_EL0_DP_BIT (U(1) << 5)
1286 #define PMCR_EL0_X_BIT (U(1) << 4)
1287 #define PMCR_EL0_D_BIT (U(1) << 3)
1288 #define PMCR_EL0_C_BIT (U(1) << 2)
1289 #define PMCR_EL0_P_BIT (U(1) << 1)
1290 #define PMCR_EL0_E_BIT (U(1) << 0)
1299 #define ZCR_EL3_LEN_MASK U(0xf)
1302 #define ZCR_EL2_LEN_MASK U(0xf)
1312 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
1313 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
1314 #define SME_FA64_IMPLEMENTED U(0x1)
1315 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
1321 #define SMCR_ELX_LEN_SHIFT U(0)
1322 #define SMCR_ELX_LEN_MAX U(0x1ff)
1323 #define SMCR_ELX_FA64_BIT (U(1) << 31)
1324 #define SMCR_ELX_EZT0_BIT (U(1) << 30)
1371 #define MAIR_NORM_OUTER_SHIFT U(4)
1377 #define PAR_F_SHIFT U(0)
1464 #define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1473 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1477 #define AMCFGR_EL0_NCG_SHIFT U(28)
1478 #define AMCFGR_EL0_NCG_MASK U(0xf)
1479 #define AMCFGR_EL0_N_SHIFT U(0)
1480 #define AMCFGR_EL0_N_MASK U(0xff)
1483 #define AMCGCR_EL0_CG0NC_SHIFT U(0)
1484 #define AMCGCR_EL0_CG0NC_MASK U(0xff)
1485 #define AMCGCR_EL0_CG1NC_SHIFT U(8)
1486 #define AMCGCR_EL0_CG1NC_MASK U(0xff)
1523 #define AMCG1IDR_CTR_SHIFT U(0)
1525 #define AMCG1IDR_VOFF_SHIFT U(16)
1528 #define AMCR_CG1RZ_SHIFT U(17)
1575 #define DISR_A_BIT U(31)
1578 #define ERRIDR_MASK U(0xffff)
1593 #define ERXCTLR_ED_SHIFT U(0)
1594 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
1595 #define ERXCTLR_UE_BIT (U(1) << 4)
1597 #define ERXPFGCTL_UC_BIT (U(1) << 1)
1598 #define ERXPFGCTL_UEU_BIT (U(1) << 2)
1599 #define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1740 #define DSU_CLUSTER_PWR_MASK U(1)
1744 #define CLUSTERPMMDCR_SPME U(1)
1770 #define CLUSTERPMCR_N_SHIFT U(11)
1771 #define CLUSTERPMCR_N_MASK U(0x1f)
1777 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf)
1778 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0)
1786 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21)
1787 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20)
1788 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19)
1789 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18)
1790 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17)
1791 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16)
1792 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15)
1793 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14)
1794 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12)
1795 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10)
1796 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9)
1797 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8)
1798 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7)
1799 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6)
1800 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5)
1801 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4)
1802 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3)
1803 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2)
1804 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1)
1805 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0)