Merge changes from topic "fix-imx8m-uart-domain-permission" into integration

* changes:
fix(imx8m): ensure domain permissions for the console
refactor(imx8m): replace UART base magic numbers wit

Merge changes from topic "fix-imx8m-uart-domain-permission" into integration

* changes:
fix(imx8m): ensure domain permissions for the console
refactor(imx8m): replace UART base magic numbers with macros

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refactor(imx8m): replace UART base magic numbers with macros

This patch replaces the magic numbers of the UART base addresses with
the corresponding macros defined in the appropriate platform file.

refactor(imx8m): replace UART base magic numbers with macros

This patch replaces the magic numbers of the UART base addresses with
the corresponding macros defined in the appropriate platform file.

Change-Id: Ie6a4555a659e9f722a8d819958ad9a2dee7c3aa0
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

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Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2

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feat(imx8mp): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if

feat(imx8mp): optionally take params from BL2

Optionally take params from BL2 to offer more flexibility to BL2 on
where and if a BL32 image is expected. This uses imx_bl31_params_parse()
to check if arg0 can safely be accessed as a pointer and actually
contains a bl_params_t structure. If not, the hardcoded parameter
values are used as before.

Change-Id: I44537ba2baa7543e459e5691b69df14b0bd6e942
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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Merge "feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE" into integration

feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE

The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is re

feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE

The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is requied. Use
this to make the platform specific PLAT_NS_IMAGE_OFFSET configurable.

This becomes necessary if one would like to place the bl33 code to other
places.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9d462c0e9df8e6d2ad78ee770bfa59e680739a51

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Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(im

Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m

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fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.co

fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd

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Merge "refactor(imx8mp): introduce BL2_SIZE and BL31_SIZE" into integration

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and map required memory blocks
feat(imx8mn): add hab and map required memory blocks
feat(imx8mm): add hab and map required memory blocks

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refactor(imx8mp): introduce BL2_SIZE and BL31_SIZE

No functional change.

Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K

refactor(imx8mp): introduce BL2_SIZE and BL31_SIZE

No functional change.

Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K to make it
easier to read. This is required for later BL31 PIE support since it
drops the calculation based on the BL31_LIMIT and BL31_BASE.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Idae34c1dfcedd35238fe083149080a199d50eed0

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feat(imx8mp): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mp): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8M+ SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I986cdce434d1ec9ea8b3c0d5599edde55b9b30f8

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Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration

* changes:
feat(imx8mp): enable BL32 fdt overlay support on imx8mp
feat(imx8mq): enable optee fdt overlay su

Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration

* changes:
feat(imx8mp): enable BL32 fdt overlay support on imx8mp
feat(imx8mq): enable optee fdt overlay support
feat(imx8mn): enable optee fdt overlay support
feat(imx8mm): enable optee fdt overlay support
feat(imx8mp): add trusty for imx8mp
feat(imx8mq): enable trusty for imx8mq
feat(imx8mn): enable Trusty OS for imx8mn
feat(imx8mm): enable Trusty OS on imx8mm
feat(imx8/imx8m): switch to xlat_tables_v2
feat(imx8m): enable the coram_s tz by default on imx8mn/mp
feat(imx8m): enable the csu init on imx8m
feat(imx8m): add a simple csu driver for imx8m family
refactor(imx8m): replace magic number with enum type
feat(imx8m): add imx csu/rdc enum type defines for imx8m
fix(imx8m): check the validation of domain id
feat(imx8m): enable conditional build for SDEI

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feat(imx8mp): enable BL32 fdt overlay support on imx8mp

Allow OP-TEE to generate a device-tree overlay binary
that will be applied by u-boot on the regular dtb.

Signed-off-by: Jacky Bai <ping.bai@n

feat(imx8mp): enable BL32 fdt overlay support on imx8mp

Allow OP-TEE to generate a device-tree overlay binary
that will be applied by u-boot on the regular dtb.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Idfd268cdd8b7ba321f8e1b9b85c2bba7ffdeddf0

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Merge "fix(imx8mp): change the BL31 physical load address" into integration

fix(imx8mp): change the BL31 physical load address

Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x97

fix(imx8mp): change the BL31 physical load address

Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x970000 is the correct value thus we change it back again.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Change-Id: Ia0db4877123b89072f723d18e2bcce25ef38f47d

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Merge changes from topic "imx8mp-tbbr" into integration

* changes:
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
refactor(plat/imx/imx8m): m

Merge changes from topic "imx8mp-tbbr" into integration

* changes:
feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common
feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout
refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common
feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

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feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and bloc

feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and block devices.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I401e48216d67257137351ee4d0b98904a76fa789

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Merge changes from topic "imx8m-sdei" into integration

* changes:
feat(plat/imx8m): add sdei support for i.MX8MP
feat(plat/imx8m): add sdei support for i.MX8MN

feat(plat/imx8m): add sdei support for i.MX8MP

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled rout

feat(plat/imx8m): add sdei support for i.MX8MP

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I8308c629448bd8adca9d3d25701adcf0c5a6afc2

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Merge changes from topic "imx8mp_fix" into integration

* changes:
plat: imx8mp: change the bl31 physical load address
plat: imx8m: Fix the macro define error

plat: imx8mp: change the bl31 physical load address

on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last

plat: imx8mp: change the bl31 physical load address

on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4

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Merge changes from topic "imx8mp_basic_support" into integration

* changes:
plat: imx8mp: Add the basic support for i.MX8MP
plat: imx8m: Move the gpc hw reg to a separate header file

plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Ma

plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a

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