Lines Matching refs:U
15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(24)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_VAR_MASK U(0xf)
20 #define MIDR_REV_SHIFT U(0)
21 #define MIDR_REV_BITS U(4)
22 #define MIDR_REV_MASK U(0xf)
23 #define MIDR_PN_MASK U(0xfff)
24 #define MIDR_PN_SHIFT U(4)
29 #define MPIDR_MT_MASK (U(1) << 24)
32 #define MPIDR_AFFINITY_BITS U(8)
33 #define MPIDR_AFFLVL_MASK U(0xff)
34 #define MPIDR_AFFLVL_SHIFT U(3)
35 #define MPIDR_AFF0_SHIFT U(0)
36 #define MPIDR_AFF1_SHIFT U(8)
37 #define MPIDR_AFF2_SHIFT U(16)
39 #define MPIDR_AFFINITY_MASK U(0x00ffffff)
40 #define MPIDR_AFFLVL0 U(0)
41 #define MPIDR_AFFLVL1 U(1)
42 #define MPIDR_AFFLVL2 U(2)
51 #define MPIDR_AFFLVL3_VAL(mpidr) U(0)
65 #define INVALID_MPID U(0xFFFFFFFF)
71 #define MPIDR_MAX_AFFLVL U(2)
74 #define DC_OP_ISW U(0x0)
75 #define DC_OP_CISW U(0x1)
79 #define DC_OP_CSW U(0x2)
85 #define CNTCR_OFF U(0x000)
87 #define CNTCVL_OFF U(0x008)
89 #define CNTCVU_OFF U(0x00C)
90 #define CNTFID_OFF U(0x020)
92 #define CNTCR_EN (U(1) << 0)
93 #define CNTCR_HDBG (U(1) << 1)
100 #define LOUIS_SHIFT U(21)
101 #define LOC_SHIFT U(24)
102 #define CLIDR_FIELD_WIDTH U(3)
105 #define LEVEL_SHIFT U(1)
108 #define ID_DFR0_PERFMON_SHIFT U(24)
109 #define ID_DFR0_PERFMON_MASK U(0xf)
110 #define ID_DFR0_PERFMON_PMUV3 U(3)
111 #define ID_DFR0_PERFMON_PMUV3P5 U(6)
112 #define ID_DFR0_COPTRC_SHIFT U(12)
113 #define ID_DFR0_COPTRC_MASK U(0xf)
114 #define COPTRC_IMPLEMENTED U(1)
115 #define ID_DFR0_COPTRC_LENGTH U(4)
116 #define ID_DFR0_TRACEFILT_SHIFT U(28)
117 #define ID_DFR0_TRACEFILT_MASK U(0xf)
118 #define TRACEFILT_IMPLEMENTED U(1)
119 #define ID_DFR0_TRACEFILT_LENGTH U(4)
122 #define ID_DFR1_MTPMU_SHIFT U(0)
123 #define ID_DFR1_MTPMU_MASK U(0xf)
124 #define MTPMU_IMPLEMENTED U(1)
125 #define MTPMU_NOT_IMPLEMENTED U(15)
128 #define ID_MMFR3_PAN_SHIFT U(16)
129 #define ID_MMFR3_PAN_MASK U(0xf)
132 #define ID_MMFR4_CNP_SHIFT U(12)
133 #define ID_MMFR4_CNP_LENGTH U(4)
134 #define ID_MMFR4_CNP_MASK U(0xf)
136 #define ID_MMFR4_CCIDX_SHIFT U(24)
137 #define ID_MMFR4_CCIDX_LENGTH U(4)
138 #define ID_MMFR4_CCIDX_MASK U(0xf)
141 #define ID_PFR0_AMU_SHIFT U(20)
142 #define ID_PFR0_AMU_LENGTH U(4)
143 #define ID_PFR0_AMU_MASK U(0xf)
144 #define ID_PFR0_AMU_V1 U(0x1)
145 #define ID_PFR0_AMU_V1P1 U(0x2)
147 #define ID_PFR0_DIT_SHIFT U(24)
148 #define ID_PFR0_DIT_LENGTH U(4)
149 #define ID_PFR0_DIT_MASK U(0xf)
150 #define DIT_IMPLEMENTED (U(1) << ID_PFR0_DIT_SHIFT)
153 #define ID_PFR1_VIRTEXT_SHIFT U(12)
154 #define ID_PFR1_VIRTEXT_MASK U(0xf)
157 #define ID_PFR1_GENTIMER_SHIFT U(16)
158 #define ID_PFR1_GENTIMER_MASK U(0xf)
159 #define ID_PFR1_GIC_SHIFT U(28)
160 #define ID_PFR1_GIC_MASK U(0xf)
161 #define ID_PFR1_SEC_SHIFT U(4)
162 #define ID_PFR1_SEC_MASK U(0xf)
163 #define ID_PFR1_ELx_ENABLED U(1)
166 #define ID_PFR2_SSBS_SHIFT U(4)
167 #define ID_PFR2_SSBS_MASK U(0xf)
168 #define SSBS_NOT_IMPLEMENTED U(0)
171 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
172 (U(1) << 3))
176 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
178 #define SCTLR_M_BIT (U(1) << 0)
179 #define SCTLR_A_BIT (U(1) << 1)
180 #define SCTLR_C_BIT (U(1) << 2)
181 #define SCTLR_CP15BEN_BIT (U(1) << 5)
182 #define SCTLR_ITD_BIT (U(1) << 7)
183 #define SCTLR_Z_BIT (U(1) << 11)
184 #define SCTLR_I_BIT (U(1) << 12)
185 #define SCTLR_V_BIT (U(1) << 13)
186 #define SCTLR_RR_BIT (U(1) << 14)
187 #define SCTLR_NTWI_BIT (U(1) << 16)
188 #define SCTLR_NTWE_BIT (U(1) << 18)
189 #define SCTLR_WXN_BIT (U(1) << 19)
190 #define SCTLR_UWXN_BIT (U(1) << 20)
191 #define SCTLR_EE_BIT (U(1) << 25)
192 #define SCTLR_TRE_BIT (U(1) << 28)
193 #define SCTLR_AFE_BIT (U(1) << 29)
194 #define SCTLR_TE_BIT (U(1) << 30)
195 #define SCTLR_DSSBS_BIT (U(1) << 31)
201 #define SDCR_SPD_LEGACY U(0x0)
202 #define SDCR_SPD_DISABLE U(0x2)
203 #define SDCR_SPD_ENABLE U(0x3)
204 #define SDCR_SPME_BIT (U(1) << 17)
205 #define SDCR_TTRF_BIT (U(1) << 19)
206 #define SDCR_SCCD_BIT (U(1) << 23)
207 #define SDCR_MTPME_BIT (U(1) << 28)
208 #define SDCR_RESET_VAL U(0x0)
211 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
212 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
213 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
215 #define HSCTLR_M_BIT (U(1) << 0)
216 #define HSCTLR_A_BIT (U(1) << 1)
217 #define HSCTLR_C_BIT (U(1) << 2)
218 #define HSCTLR_CP15BEN_BIT (U(1) << 5)
219 #define HSCTLR_ITD_BIT (U(1) << 7)
220 #define HSCTLR_SED_BIT (U(1) << 8)
221 #define HSCTLR_I_BIT (U(1) << 12)
222 #define HSCTLR_WXN_BIT (U(1) << 19)
223 #define HSCTLR_EE_BIT (U(1) << 25)
224 #define HSCTLR_TE_BIT (U(1) << 30)
245 #define SCR_VALID_BIT_MASK U(0x33ff)
246 #define SCR_RESET_VAL U(0x0)
251 #define HCR_TGE_BIT (U(1) << 27)
252 #define HCR_AMO_BIT (U(1) << 5)
253 #define HCR_IMO_BIT (U(1) << 4)
254 #define HCR_FMO_BIT (U(1) << 3)
255 #define HCR_RESET_VAL U(0x0)
258 #define CNTHCTL_RESET_VAL U(0x0)
259 #define PL1PCEN_BIT (U(1) << 1)
260 #define PL1PCTEN_BIT (U(1) << 0)
263 #define PL0PTEN_BIT (U(1) << 9)
264 #define PL0VTEN_BIT (U(1) << 8)
265 #define PL0PCTEN_BIT (U(1) << 0)
266 #define PL0VCTEN_BIT (U(1) << 1)
267 #define EVNTEN_BIT (U(1) << 2)
268 #define EVNTDIR_BIT (U(1) << 3)
269 #define EVNTI_SHIFT U(4)
270 #define EVNTI_MASK U(0xf)
273 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
274 #define TCPAC_BIT (U(1) << 31)
275 #define TAM_SHIFT U(30)
276 #define TAM_BIT (U(1) << TAM_SHIFT)
277 #define TTA_BIT (U(1) << 20)
278 #define TCP11_BIT (U(1) << 11)
279 #define TCP10_BIT (U(1) << 10)
285 #define VTTBR_VMID_SHIFT U(48)
287 #define VTTBR_BADDR_SHIFT U(0)
290 #define HDCR_MTPME_BIT (U(1) << 28)
291 #define HDCR_HLP_BIT (U(1) << 26)
292 #define HDCR_HPME_BIT (U(1) << 7)
293 #define HDCR_RESET_VAL U(0x0)
296 #define HSTR_RESET_VAL U(0x0)
299 #define CNTHP_CTL_RESET_VAL U(0x0)
302 #define NSASEDIS_BIT (U(1) << 15)
303 #define NSTRCDIS_BIT (U(1) << 20)
304 #define NSACR_CP11_BIT (U(1) << 11)
305 #define NSACR_CP10_BIT (U(1) << 10)
306 #define NSACR_IMP_DEF_MASK (U(0x7) << 16)
308 #define NSACR_RESET_VAL U(0x0)
311 #define ASEDIS_BIT (U(1) << 31)
312 #define TRCDIS_BIT (U(1) << 28)
313 #define CPACR_CP11_SHIFT U(22)
314 #define CPACR_CP10_SHIFT U(20)
315 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
316 (U(0x3) << CPACR_CP10_SHIFT))
317 #define CPACR_RESET_VAL U(0x0)
320 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
321 #define FPEXC_EN_BIT (U(1) << 30)
325 #define SPSR_FIQ_BIT (U(1) << 0)
326 #define SPSR_IRQ_BIT (U(1) << 1)
327 #define SPSR_ABT_BIT (U(1) << 2)
328 #define SPSR_AIF_SHIFT U(6)
329 #define SPSR_AIF_MASK U(0x7)
331 #define SPSR_E_SHIFT U(9)
332 #define SPSR_E_MASK U(0x1)
333 #define SPSR_E_LITTLE U(0)
334 #define SPSR_E_BIG U(1)
336 #define SPSR_T_SHIFT U(5)
337 #define SPSR_T_MASK U(0x1)
338 #define SPSR_T_ARM U(0)
339 #define SPSR_T_THUMB U(1)
341 #define SPSR_MODE_SHIFT U(0)
342 #define SPSR_MODE_MASK U(0x7)
349 #define CPSR_DIT_BIT (U(1) << 21)
353 #define TTBCR_EAE_BIT (U(1) << 31)
355 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
356 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
357 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
359 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
360 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
361 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
362 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
364 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
365 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
366 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
367 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
369 #define TTBCR_EPD1_BIT (U(1) << 23)
370 #define TTBCR_A1_BIT (U(1) << 22)
372 #define TTBCR_T1SZ_SHIFT U(16)
373 #define TTBCR_T1SZ_MASK U(0x7)
374 #define TTBCR_TxSZ_MIN U(0)
375 #define TTBCR_TxSZ_MAX U(7)
377 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
378 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
379 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
381 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
382 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
383 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
384 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
386 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
387 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
388 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
389 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
391 #define TTBCR_EPD0_BIT (U(1) << 7)
392 #define TTBCR_T0SZ_SHIFT U(0)
393 #define TTBCR_T0SZ_MASK U(0x7)
398 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
400 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
401 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
402 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
404 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
405 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
406 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
407 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
409 #define HTCR_RGN0_INNER_NC (U(0x0) << 8)
410 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
411 #define HTCR_RGN0_INNER_WT (U(0x2) << 8)
412 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
414 #define HTCR_T0SZ_SHIFT U(0)
415 #define HTCR_T0SZ_MASK U(0x7)
417 #define MODE_RW_SHIFT U(0x4)
418 #define MODE_RW_MASK U(0x1)
419 #define MODE_RW_32 U(0x1)
421 #define MODE32_SHIFT U(0)
422 #define MODE32_MASK U(0x1f)
423 #define MODE32_usr U(0x10)
424 #define MODE32_fiq U(0x11)
425 #define MODE32_irq U(0x12)
426 #define MODE32_svc U(0x13)
427 #define MODE32_mon U(0x16)
428 #define MODE32_abt U(0x17)
429 #define MODE32_hyp U(0x1a)
430 #define MODE32_und U(0x1b)
431 #define MODE32_sys U(0x1f)
455 #define CTR_CWG_SHIFT U(24)
456 #define CTR_CWG_MASK U(0xf)
457 #define CTR_ERG_SHIFT U(20)
458 #define CTR_ERG_MASK U(0xf)
459 #define CTR_DMINLINE_SHIFT U(16)
460 #define CTR_DMINLINE_WIDTH U(4)
461 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
462 #define CTR_L1IP_SHIFT U(14)
463 #define CTR_L1IP_MASK U(0x3)
464 #define CTR_IMINLINE_SHIFT U(0)
465 #define CTR_IMINLINE_MASK U(0xf)
467 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
470 #define PMCR_N_SHIFT U(11)
471 #define PMCR_N_MASK U(0x1f)
473 #define PMCR_LP_BIT (U(1) << 7)
474 #define PMCR_LC_BIT (U(1) << 6)
475 #define PMCR_DP_BIT (U(1) << 5)
476 #define PMCR_X_BIT (U(1) << 4)
477 #define PMCR_C_BIT (U(1) << 2)
478 #define PMCR_P_BIT (U(1) << 1)
479 #define PMCR_E_BIT (U(1) << 0)
480 #define PMCR_RESET_VAL U(0x0)
487 #define TLBI_ADDR_SHIFT U(0)
488 #define TLBI_ADDR_MASK U(0xFFFFF000)
495 #define CNTCTLBASE_CNTFRQ U(0x0)
496 #define CNTNSAR U(0x4)
499 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
500 #define CNTACR_RPCT_SHIFT U(0x0)
501 #define CNTACR_RVCT_SHIFT U(0x1)
502 #define CNTACR_RFRQ_SHIFT U(0x2)
503 #define CNTACR_RVOFF_SHIFT U(0x3)
504 #define CNTACR_RWVT_SHIFT U(0x4)
505 #define CNTACR_RWPT_SHIFT U(0x5)
512 #define CNTPCT_LO U(0x0)
514 #define CNTBASEN_CNTFRQ U(0x10)
516 #define CNTP_CVAL_LO U(0x20)
518 #define CNTP_CTL U(0x2c)
525 #define CNTP_CTL_ENABLE_MASK U(1)
526 #define CNTP_CTL_IMASK_MASK U(1)
527 #define CNTP_CTL_ISTATUS_MASK U(1)
530 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
531 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
653 #define MAIR_DEV_nGnRnE U(0x0)
654 #define MAIR_DEV_nGnRE U(0x4)
655 #define MAIR_DEV_nGRE U(0x8)
656 #define MAIR_DEV_GRE U(0xc)
676 #define MAIR_NORM_WT_TR_WA U(0x1)
677 #define MAIR_NORM_WT_TR_RA U(0x2)
678 #define MAIR_NORM_WT_TR_RWA U(0x3)
679 #define MAIR_NORM_NC U(0x4)
680 #define MAIR_NORM_WB_TR_WA U(0x5)
681 #define MAIR_NORM_WB_TR_RA U(0x6)
682 #define MAIR_NORM_WB_TR_RWA U(0x7)
683 #define MAIR_NORM_WT_NTR_NA U(0x8)
684 #define MAIR_NORM_WT_NTR_WA U(0x9)
685 #define MAIR_NORM_WT_NTR_RA U(0xa)
686 #define MAIR_NORM_WT_NTR_RWA U(0xb)
687 #define MAIR_NORM_WB_NTR_NA U(0xc)
688 #define MAIR_NORM_WB_NTR_WA U(0xd)
689 #define MAIR_NORM_WB_NTR_RA U(0xe)
690 #define MAIR_NORM_WB_NTR_RWA U(0xf)
692 #define MAIR_NORM_OUTER_SHIFT U(4)
698 #define PAR_F_SHIFT U(0)
763 #define AMCNTENSET0_Pn_SHIFT U(0)
764 #define AMCNTENSET0_Pn_MASK U(0xf)
767 #define AMCNTENSET1_Pn_SHIFT U(0)
768 #define AMCNTENSET1_Pn_MASK U(0xffff)
771 #define AMCNTENCLR0_Pn_SHIFT U(0)
772 #define AMCNTENCLR0_Pn_MASK U(0xf)
775 #define AMCNTENCLR1_Pn_SHIFT U(0)
776 #define AMCNTENCLR1_Pn_MASK U(0xffff)
779 #define AMCR_CG1RZ_SHIFT U(17)
783 #define AMCFGR_NCG_SHIFT U(28)
784 #define AMCFGR_NCG_MASK U(0xf)
785 #define AMCFGR_N_SHIFT U(0)
786 #define AMCFGR_N_MASK U(0xff)
789 #define AMCGCR_CG0NC_SHIFT U(0)
790 #define AMCGCR_CG0NC_MASK U(0xff)
791 #define AMCGCR_CG1NC_SHIFT U(8)
792 #define AMCGCR_CG1NC_MASK U(0xff)
810 #define CLUSTERPMCR_N_SHIFT U(11)
811 #define CLUSTERPMCR_N_MASK U(0x1f)
817 #define DSU_CLUSTER_PWR_MASK U(1)
821 #define CLUSTERPMMDCR_SPME U(1)