Lines Matching refs:U
18 #define RCAR_SHARED_MEM_SIZE U(0x00001000)
19 #define FLASH0_BASE U(0x08000000)
20 #define FLASH0_SIZE U(0x04000000)
21 #define FLASH_MEMORY_SIZE U(0x04000000) /* hyper flash */
22 #define FLASH_TRANS_SIZE_UNIT U(0x00000100)
23 #define DEVICE_RCAR_BASE U(0xE6000000)
24 #define DEVICE_RCAR_SIZE U(0x00300000)
25 #define DEVICE_RCAR_BASE2 U(0xE6360000)
26 #define DEVICE_RCAR_SIZE2 U(0x19CA0000)
27 #define DEVICE_SRAM_BASE U(0xE6300000)
28 #define DEVICE_SRAM_SIZE U(0x00002000)
30 #define DEVICE_SRAM_STACK_SIZE U(0x00001000)
32 #define DRAM1_BASE U(0x40000000)
33 #define DRAM1_SIZE U(0x80000000)
34 #define DRAM1_NS_BASE (DRAM1_BASE + U(0x08000000))
41 #define RCAR_BL31_CRASH_BASE U(0x4403F000)
42 #define RCAR_BL31_CRASH_SIZE U(0x00001000)
70 #define REG1_BASE U(0xE6400000)
71 #define REG1_SIZE U(0x04C00000)
72 #define ROM0_BASE U(0xEB100000)
73 #define ROM0_SIZE U(0x00028000)
74 #define REG2_BASE U(0xEC000000)
75 #define REG2_SIZE U(0x14000000)
78 #define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000))
92 #define CCI500_BASE U(0xF1200000)
99 #define RCAR_GICD_BASE U(0xF1010000)
100 #define RCAR_GICR_BASE U(0xF1010000)
101 #define RCAR_GICC_BASE U(0xF1020000)
102 #define RCAR_GICH_BASE U(0xF1040000)
103 #define RCAR_GICV_BASE U(0xF1060000)
104 #define ARM_IRQ_SEC_PHY_TIMER U(29)
105 #define ARM_IRQ_SEC_SGI_0 U(8)
106 #define ARM_IRQ_SEC_SGI_1 U(9)
107 #define ARM_IRQ_SEC_SGI_2 U(10)
108 #define ARM_IRQ_SEC_SGI_3 U(11)
109 #define ARM_IRQ_SEC_SGI_4 U(12)
110 #define ARM_IRQ_SEC_SGI_5 U(13)
111 #define ARM_IRQ_SEC_SGI_6 U(14)
112 #define ARM_IRQ_SEC_SGI_7 U(15)
113 #define ARM_IRQ_SEC_RPC U(70)
114 #define ARM_IRQ_SEC_TIMER U(166)
115 #define ARM_IRQ_SEC_TIMER_UP U(171)
116 #define ARM_IRQ_SEC_WDT U(173)
117 #define ARM_IRQ_SEC_CRYPT U(102)
118 #define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
119 #define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
121 #define RCAR_CNTC_BASE U(0xE6080000)
123 #define RCAR_MODEMR U(0xE6160060) /* Mode pin */
124 #define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
125 #define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
126 #define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
127 #define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
128 #define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
129 #define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
130 #define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
131 #define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
132 #define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
133 #define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
134 #define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
135 #define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
136 #define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
138 #define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
139 #define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
140 #define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
141 #define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
142 #define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
143 #define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
144 #define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
145 #define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
146 #define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
147 #define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
148 #define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
149 #define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
150 #define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
151 #define RCAR_SYSCEXTMASK U(0xE61802F8) /* External Request Mask */
154 #define RCAR_PRR U(0xFFF00044)
155 #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
156 #define RCAR_D3_CUT_VER10 U(0x00000000) /* D3 Ver.1.0 */
157 #define RCAR_D3_CUT_VER11 U(0x00000010) /* D3 Ver.1.1 */
158 #define RCAR_MAJOR_MASK U(0x000000F0)
159 #define RCAR_MINOR_MASK U(0x0000000F)
160 #define PRR_PRODUCT_SHIFT U(8)
161 #define RCAR_MAJOR_SHIFT U(4)
162 #define RCAR_MINOR_SHIFT U(0)
163 #define RCAR_MAJOR_OFFSET U(1)
164 #define RCAR_M3_MINOR_OFFSET U(2)
165 #define PRR_PRODUCT_H3_CUT10 (PRR_PRODUCT_H3 | U(0x00)) /* 1.0 */
166 #define PRR_PRODUCT_H3_CUT11 (PRR_PRODUCT_H3 | U(0x01)) /* 1.1 */
167 #define PRR_PRODUCT_H3_CUT20 (PRR_PRODUCT_H3 | U(0x10)) /* 2.0 */
168 #define PRR_PRODUCT_M3_CUT10 (PRR_PRODUCT_M3 | U(0x00)) /* 1.0 */
169 #define PRR_PRODUCT_M3_CUT11 (PRR_PRODUCT_M3 | U(0x10))
185 #define RCAR_CPU_MASK_CA57 U(0x80000000)
186 #define RCAR_CPU_MASK_CA53 U(0x04000000)
187 #define RCAR_CPU_HAVE_CA57 U(0x00000000)
188 #define RCAR_CPU_HAVE_CA53 U(0x00000000)
189 #define RCAR_SSCG_MASK U(0x1000) /* MD12 */
190 #define RCAR_SSCG_ENABLE U(0x1000)
192 #define MODEMR_BOOT_CPU_MASK U(0x000000C0)
193 #define MODEMR_BOOT_CPU_CR7 U(0x000000C0)
194 #define MODEMR_BOOT_CPU_CA57 U(0x00000000)
195 #define MODEMR_BOOT_CPU_CA53 U(0x00000040)
196 #define MODEMR_BOOT_DEV_MASK U(0x0000001E)
197 #define MODEMR_BOOT_DEV_HYPERFLASH160 U(0x00000004)
198 #define MODEMR_BOOT_DEV_HYPERFLASH80 U(0x00000006)
199 #define MODEMR_BOOT_DEV_QSPI_FLASH40 U(0x00000008)
200 #define MODEMR_BOOT_DEV_QSPI_FLASH80 U(0x0000000C)
201 #define MODEMR_BOOT_DEV_EMMC_25X1 U(0x0000000A)
202 #define MODEMR_BOOT_DEV_EMMC_50X8 U(0x0000001A)
203 #define MODEMR_BOOT_PLL_MASK U(0x00006000)
204 #define MODEMR_BOOT_PLL_SHIFT U(13)
208 #define CHECK_MD13_MD14 U(0x6000)
209 #define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
210 #define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
211 #define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
212 #define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
214 #define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
215 #define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
216 #define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
217 #define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
218 #define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
219 #define EXTAL_EBISU U(24000000) /* Ebisu */
220 #define EXTAL_DRAAK U(24000000) /* Draak */
237 #define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)