Lines Matching refs:U
54 #define STM32MP2_CHIP_ID U(0x505)
56 #define STM32MP251A_PART_NB U(0x400B3E6D)
57 #define STM32MP251C_PART_NB U(0x000B306D)
58 #define STM32MP251D_PART_NB U(0xC00B3E6D)
59 #define STM32MP251F_PART_NB U(0x800B306D)
60 #define STM32MP253A_PART_NB U(0x400B3E0C)
61 #define STM32MP253C_PART_NB U(0x000B300C)
62 #define STM32MP253D_PART_NB U(0xC00B3E0C)
63 #define STM32MP253F_PART_NB U(0x800B300C)
64 #define STM32MP255A_PART_NB U(0x40082E00)
65 #define STM32MP255C_PART_NB U(0x00082000)
66 #define STM32MP255D_PART_NB U(0xC0082E00)
67 #define STM32MP255F_PART_NB U(0x80082000)
68 #define STM32MP257A_PART_NB U(0x40002E00)
69 #define STM32MP257C_PART_NB U(0x00002000)
70 #define STM32MP257D_PART_NB U(0xC0002E00)
71 #define STM32MP257F_PART_NB U(0x80002000)
73 #define STM32MP2_REV_A U(0x08)
74 #define STM32MP2_REV_B U(0x10)
75 #define STM32MP2_REV_X U(0x12)
76 #define STM32MP2_REV_Y U(0x11)
77 #define STM32MP2_REV_Z U(0x09)
82 #define STM32MP25_PKG_CUSTOM U(0)
83 #define STM32MP25_PKG_AL_VFBGA361 U(1)
84 #define STM32MP25_PKG_AK_VFBGA424 U(3)
85 #define STM32MP25_PKG_AI_TFBGA436 U(5)
86 #define STM32MP25_PKG_UNKNOWN U(7)
91 #define STM32MP_SYSRAM_BASE U(0x0E000000)
92 #define STM32MP_SYSRAM_SIZE U(0x00040000)
93 #define SRAM1_BASE U(0x0E040000)
94 #define SRAM1_SIZE_FOR_TFA U(0x00010000)
95 #define RETRAM_BASE U(0x0E080000)
96 #define RETRAM_SIZE U(0x00020000)
113 #define STM32MP_DDR_BASE U(0x80000000)
126 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
128 #define STM32MP_HEADER_SIZE U(0x00000200)
133 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
143 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
144 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
164 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
177 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
189 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400)
190 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800)
191 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
197 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
198 #define STM32MP_BL33_MAX_SIZE U(0x400000)
201 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
202 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */
207 #define STM32MP_DEVICE_BASE U(0x40000000)
208 #define STM32MP_DEVICE_SIZE U(0x40000000)
213 #define RCC_BASE U(0x44200000)
218 #define PWR_BASE U(0x44210000)
223 #define GPIOA_BASE U(0x44240000)
224 #define GPIOB_BASE U(0x44250000)
225 #define GPIOC_BASE U(0x44260000)
226 #define GPIOD_BASE U(0x44270000)
227 #define GPIOE_BASE U(0x44280000)
228 #define GPIOF_BASE U(0x44290000)
229 #define GPIOG_BASE U(0x442A0000)
230 #define GPIOH_BASE U(0x442B0000)
231 #define GPIOI_BASE U(0x442C0000)
232 #define GPIOJ_BASE U(0x442D0000)
233 #define GPIOK_BASE U(0x442E0000)
234 #define GPIOZ_BASE U(0x46200000)
235 #define GPIO_BANK_OFFSET U(0x10000)
243 #define USART1_BASE U(0x40330000)
244 #define USART2_BASE U(0x400E0000)
245 #define USART3_BASE U(0x400F0000)
246 #define UART4_BASE U(0x40100000)
247 #define UART5_BASE U(0x40110000)
248 #define USART6_BASE U(0x40220000)
249 #define UART7_BASE U(0x40370000)
250 #define UART8_BASE U(0x40380000)
251 #define UART9_BASE U(0x402C0000)
252 #define STM32MP_NB_OF_UART U(9)
292 #define STM32MP_SDMMC1_BASE U(0x48220000)
293 #define STM32MP_SDMMC2_BASE U(0x48230000)
294 #define STM32MP_SDMMC3_BASE U(0x48240000)
300 #define STM32MP_OSPI_MM_BASE U(0x60000000)
301 #define STM32MP_OSPI_MM_SIZE U(0x10000000)
311 #define STM32MP2_OTP_MAX_ID U(0x16F)
312 #define STM32MP2_MID_OTP_START U(0x80)
313 #define STM32MP2_UPPER_OTP_START U(0x100)
331 #define PACKAGE_OTP_PKG_SHIFT U(0)
334 #define HCONF1_OTP_IWDG_HW_POS U(0)
335 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
336 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
344 #define NAND_PAGE_SIZE_SHIFT U(29)
345 #define NAND_PAGE_SIZE_2K U(0)
346 #define NAND_PAGE_SIZE_4K U(1)
347 #define NAND_PAGE_SIZE_8K U(2)
351 #define NAND_BLOCK_SIZE_SHIFT U(27)
352 #define NAND_BLOCK_SIZE_64_PAGES U(0)
353 #define NAND_BLOCK_SIZE_128_PAGES U(1)
354 #define NAND_BLOCK_SIZE_256_PAGES U(2)
358 #define NAND_BLOCK_NB_SHIFT U(19)
359 #define NAND_BLOCK_NB_UNIT U(256)
363 #define NAND_WIDTH_SHIFT U(18)
367 #define NAND_ECC_BIT_NB_SHIFT U(15)
368 #define NAND_ECC_BIT_NB_UNSET U(0)
369 #define NAND_ECC_BIT_NB_1_BITS U(1)
370 #define NAND_ECC_BIT_NB_4_BITS U(2)
371 #define NAND_ECC_BIT_NB_8_BITS U(3)
372 #define NAND_ECC_ON_DIE U(4)
378 #define NAND2_PAGE_SIZE_SHIFT U(16)
382 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
383 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
386 #define MAX_MONOTONIC_VALUE U(32)
389 #define UID_WORD_NB U(3)
397 #define PLAT_MAX_TAMP_INT U(5)
398 #define PLAT_MAX_TAMP_EXT U(3)
399 #define TAMP_BASE U(0x46010000)
400 #define TAMP_SMCR (TAMP_BASE + U(0x20))
401 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
403 #define TAMP_BKP_SEC_NUMBER U(10)
404 #define TAMP_COUNTR U(0x40)
416 #define USB_DWC3_BASE U(0x48300000)
421 #define DDRCTRL_BASE U(0x48040000)
426 #define DDRDBG_BASE U(0x48050000)
431 #define DDRPHYC_BASE U(0x48C00000)
436 #define BSEC_BASE U(0x44000000)
437 #define DBGMCU_BASE U(0x4A010000)
438 #define HASH_BASE U(0x42010000)
439 #define RTC_BASE U(0x46000000)
440 #define STGEN_BASE U(0x48080000)
441 #define SYSCFG_BASE U(0x44230000)
446 #define RIFSC_BASE U(0x42080000)
447 #define RISAB1_BASE U(0x420F0000)
448 #define RISAB2_BASE U(0x42100000)
449 #define RISAB3_BASE U(0x42110000)
450 #define RISAB5_BASE U(0x42130000)
458 #define RISAF1_BASE U(0x420A0000)
459 #define RISAF2_BASE U(0x420B0000)
460 #define RISAF4_BASE U(0x420D0000)
461 #define RISAF5_BASE U(0x420E0000)
491 #define RISAF_SEED_SIZE_IN_BYTES U(4)
496 #define STM32MP2_RIMU_USB3DR U(4)
508 #define A35SSC_BASE U(0x48800000)
514 #define PLAT_NB_RDEVS U(19)
516 #define PLAT_NB_FIXED_REGUS U(2)
518 #define PLAT_NB_GPIO_REGUS U(0)