Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge changes from topic "tegra-downstream-08282020" into integration

* changes:
Tegra: platform specific BL31_SIZE
Tegra186: sanity check power state type
Tegra: fixup CNTPS_TVAL_EL1 delay ti

Merge changes from topic "tegra-downstream-08282020" into integration

* changes:
Tegra: platform specific BL31_SIZE
Tegra186: sanity check power state type
Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
Tegra: add platform specific 'runtime_setup' handler
Tegra: remove ENABLE_SVE_FOR_NS = 0
lib: cpus: denver: add MIDR PN9 variant
cpus: denver: introduce macro to declare cpu_ops

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Tegra: platform specific BL31_SIZE

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-b

Tegra: platform specific BL31_SIZE

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82

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Merge changes from topic "tegra-downstream-08252020" into integration

* changes:
Tegra194: remove unused tegra_mc_defs header
Tegra: memctrl: platform setup handler functions
Tegra194: memctrl

Merge changes from topic "tegra-downstream-08252020" into integration

* changes:
Tegra194: remove unused tegra_mc_defs header
Tegra: memctrl: platform setup handler functions
Tegra194: memctrl: remove streamid security cfg registers
Tegra194: memctrl: remove streamid override cfg registers
Tegra: debug prints indicating SC7 entry sequence completion
Tegra194: add strict checking mode verification
Tegra194: memctrl: update TZDRAM base at 1MB granularity
Tegra194: ras: split up RAS error clear SMC call.
Tegra: platform specific GIC sources
Tegra194: add memory barriers during DRAM to SysRAM copy
Tegra: sip: add VPR resize enabled check
Tegra194: add redundancy checks for MMIO writes
Tegra: remove unused cortex_a53.h
Tegra194: report failure to enable dual execution
Tegra194: verify firewall settings before resource use

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Tegra: sip: add VPR resize enabled check

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which

Tegra: sip: add VPR resize enabled check

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Merge changes from topic "tegra-downstream-03102020" into integration

* changes:
Tegra210: Remove "unsupported func ID" error msg
Tegra210: support for secure physical timer
spd: tlkd: secure

Merge changes from topic "tegra-downstream-03102020" into integration

* changes:
Tegra210: Remove "unsupported func ID" error msg
Tegra210: support for secure physical timer
spd: tlkd: secure timer interrupt handler
Tegra: smmu: export handlers to read/write SMMU registers
Tegra: smmu: remove context save sequence
Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
Tegra194: memctrl: lock some more MC SID security configs
Tegra194: add SE support to generate SHA256 of TZRAM
Tegra194: store TZDRAM base/size to scratch registers
Tegra194: fix warnings for extra parentheses

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Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS

Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, wa

Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "tegra-downstream-02182020" into integration

* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegr

Merge changes from topic "tegra-downstream-02182020" into integration

* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegra186: add support for bpmp_ipc driver
Tegra210: disable ERRATA_A57_829520
Tegra194: memctrl: add support for MIU4 and MIU5
Tegra194: memctrl: remove support to reconfigure MSS
Tegra: fiq_glue: remove bakery locks from interrupt handler
Tegra210: SE: add context save support
Tegra210: update the PMC blacklisted registers
Tegra: disable CPUACTLR access from lower exception levels
cpus: denver: fixup register used to store return address

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Tegra186: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
s

Tegra186: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra186: add support for bpmp_ipc driver

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818a

Tegra186: add support for bpmp_ipc driver

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Merge changes from topic "tegra-downstream-01242020" into integration

* changes:
Tegra186: memctrl: lock stream id security config
Tegra194: remove support for simulated system suspend
Tegra19

Merge changes from topic "tegra-downstream-01242020" into integration

* changes:
Tegra186: memctrl: lock stream id security config
Tegra194: remove support for simulated system suspend
Tegra194: mce: fix multiple MISRA issues
Tegra: bpmp: fix multiple MISRA issues
Tegra194: se: fix multiple MISRA issues
Tegra: compile PMC driver for Tegra132/Tegra210 platforms
Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler
Tegra: remove weakly defined per-platform SiP handler
Tegra: remove weakly defined PSCI platform handlers
Tegra: remove weakly defined platform setup handlers
Tegra: per-SoC DRAM base values

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Tegra: per-SoC DRAM base values

Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC header

Tegra: per-SoC DRAM base values

Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.

Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19

Tf2.0 tegra downstream rebase 1.25.19

Tegra: platform dependent address space sizes

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the pla

Tegra: platform dependent address space sizes

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.

Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There

Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Merge pull request #1776 from vwadekar/tf2.0-tegra-downstream-rebase-1.22.19

Tf2.0 tegra downstream rebase 1.22.19

Tegra: rename secure scratch register macros

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* ->

Tegra: rename secure scratch register macros

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: memctrl_v2: allow CPU accesses to TZRAM

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360e

Tegra: memctrl_v2: allow CPU accesses to TZRAM

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exitin

Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.

Change-Id: Id76175c2a7d931227589468511365599e2908411
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19

Tf2.0 tegra downstream rebase 1.7.19

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for t

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra: common: drivers: fix MISRA defects

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operatio

Tegra: common: drivers: fix MISRA defects

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operation [Rule 12.4]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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