Lines Matching refs:U
16 #define PLAT_PRIMARY_CPU U(0x0)
17 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
18 #define PLATFORM_CLUSTER_COUNT U(1)
19 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
20 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
27 #define PWR_DOMAIN_AT_MAX_LVL U(1)
28 #define PLAT_MAX_PWR_LVL U(2)
29 #define PLAT_MAX_OFF_STATE U(4)
30 #define PLAT_MAX_RET_STATE U(1)
33 #define PLAT_WAIT_OFF_STATE U(2)
34 #define PLAT_STOP_OFF_STATE U(3)
36 #define BL31_BASE U(0x910000)
40 #define OCRAM_S_BASE U(0x180000)
48 #define PLAT_NS_IMAGE_OFFSET U(0x40200000)
53 #define PLAT_GICD_BASE U(0x38800000)
54 #define PLAT_GICR_BASE U(0x38880000)
67 #define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */
74 #define IMX_UART1_BASE U(0x30860000)
75 #define IMX_UART2_BASE U(0x30890000)
76 #define IMX_UART3_BASE U(0x30880000)
77 #define IMX_UART4_BASE U(0x30a60000)
79 #define IMX_AIPS_BASE U(0x30200000)
80 #define IMX_AIPS_SIZE U(0xC00000)
81 #define IMX_AIPS1_BASE U(0x30200000)
82 #define IMX_AIPS3_ARB_BASE U(0x30800000)
83 #define IMX_OCOTP_BASE U(0x30350000)
84 #define IMX_ANAMIX_BASE U(0x30360000)
85 #define IMX_CCM_BASE U(0x30380000)
86 #define IMX_SRC_BASE U(0x30390000)
87 #define IMX_GPC_BASE U(0x303a0000)
88 #define IMX_RDC_BASE U(0x303d0000)
89 #define IMX_CSU_BASE U(0x303e0000)
90 #define IMX_WDOG_BASE U(0x30280000)
91 #define IMX_SNVS_BASE U(0x30370000)
92 #define IMX_NOC_BASE U(0x32700000)
93 #define IMX_TZASC_BASE U(0x32F80000)
94 #define IMX_CAAM_BASE U(0x30900000)
95 #define IMX_IOMUX_GPR_BASE U(0x30340000)
96 #define IMX_DDRC_BASE U(0x3d400000)
97 #define IMX_DDRPHY_BASE U(0x3c000000)
98 #define IMX_DDR_IPS_BASE U(0x3d000000)
99 #define IMX_DDR_IPS_SIZE U(0x1800000)
100 #define IMX_DRAM_BASE U(0x40000000)
101 #define IMX_DRAM_SIZE U(0xc0000000)
102 #define IMX_NS_OCRAM_BASE U(0x900000)
103 #define IMX_NS_OCRAM_SIZE U(0x20000)
104 #define IMX_CAAM_RAM_BASE U(0x100000)
105 #define IMX_CAAM_RAM_SIZE U(0x10000)
106 #define IMX_ROM_BASE U(0x00000000)
107 #define IMX_ROM_SIZE U(0x20000)
109 #define AIPSTZ1_BASE U(0x301f0000)
110 #define AIPSTZ2_BASE U(0x305f0000)
111 #define AIPSTZ3_BASE U(0x309f0000)
112 #define AIPSTZ4_BASE U(0x32df0000)
114 #define GPV_BASE U(0x32000000)
115 #define GPV_SIZE U(0x800000)
117 #define IMX_GIC_SIZE U(0x200000)
119 #define WDOG_WSR U(0x2)
129 #define SRC_A53RCR0 U(0x4)
130 #define SRC_A53RCR1 U(0x8)
131 #define SRC_OTG1PHY_SCR U(0x20)
132 #define SRC_OTG2PHY_SCR U(0x24)
133 #define SRC_GPR1_OFFSET U(0x74)
134 #define SRC_GPR10_OFFSET U(0x98)
137 #define SNVS_LPCR U(0x38)
142 #define SAVED_DRAM_TIMING_BASE U(0x40000000)
149 #define IOMUXC_GPR10 U(0x28)