Lines Matching refs:U
14 #define NXP_IFC_RUN_TIME_ADDR U(0x1000)
17 #define EXT_CSPR(n) (U(0x000C) + (n * 0xC))
18 #define CSPR(n) (U(0x0010) + (n * 0xC))
19 #define CSOR(n) (U(0x0130) + (n * 0xC))
20 #define EXT_CSOR(n) (U(0x0134) + (n * 0xC))
21 #define IFC_AMASK_CS0 U(0x00A0)
24 #define NCFGR (NXP_IFC_RUN_TIME_ADDR + U(0x0000))
25 #define NAND_FCR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0014))
27 #define ROW0 (NXP_IFC_RUN_TIME_ADDR + U(0x003C))
28 #define ROW1 (NXP_IFC_RUN_TIME_ADDR + U(0x004C))
29 #define COL0 (NXP_IFC_RUN_TIME_ADDR + U(0x0044))
30 #define COL1 (NXP_IFC_RUN_TIME_ADDR + U(0x0054))
32 #define NAND_BC (NXP_IFC_RUN_TIME_ADDR + U(0x0108))
33 #define NAND_FIR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0110))
34 #define NAND_FIR1 (NXP_IFC_RUN_TIME_ADDR + U(0x0114))
35 #define NAND_FIR2 (NXP_IFC_RUN_TIME_ADDR + U(0x0118))
36 #define NAND_CSEL (NXP_IFC_RUN_TIME_ADDR + U(0x015C))
37 #define NANDSEQ_STRT (NXP_IFC_RUN_TIME_ADDR + U(0x0164))
38 #define NAND_EVTER_STAT (NXP_IFC_RUN_TIME_ADDR + U(0x016C))
39 #define NAND_AUTOBOOT_TRGR (NXP_IFC_RUN_TIME_ADDR + U(0x0284))
42 #define CSPR_PS U(0x00000180)
49 #define CSOR_NAND_PGS U(0x00380000)
51 #define CSOR_NAND_PGS_512 U(0x00000000)
52 #define CSOR_NAND_PGS_2K U(0x00080000)
53 #define CSOR_NAND_PGS_4K U(0x00100000)
54 #define CSOR_NAND_PGS_8K U(0x00180000)
55 #define CSOR_NAND_PGS_16K U(0x00200000)
58 #define CSOR_NAND_PB U(0x00000700)
59 #define CSOR_NAND_PB_32 U(0x00000000)
60 #define CSOR_NAND_PB_64 U(0x00000100)
61 #define CSOR_NAND_PB_128 U(0x00000200)
62 #define CSOR_NAND_PB_256 U(0x00000300)
63 #define CSOR_NAND_PB_512 U(0x00000400)
64 #define CSOR_NAND_PB_1024 U(0x00000500)
65 #define CSOR_NAND_PB_2048 U(0x00000600)
79 #define FCR_CMD0 U(0xFF000000)
81 #define FCR_CMD1 U(0x00FF0000)
83 #define FCR_CMD2 U(0x0000FF00)
85 #define FCR_CMD3 U(0x000000FF)
89 #define FIR_OP0 U(0xFC000000)
91 #define FIR_OP1 U(0x03F00000)
93 #define FIR_OP2 U(0x000FC000)
95 #define FIR_OP3 U(0x00003F00)
97 #define FIR_OP4 U(0x000000FC)
99 #define FIR_OP5 U(0xFC000000)
101 #define FIR_OP6 U(0x03F00000)
125 #define NAND_SEQ_STRT_FIR_STRT U(0x80000000)
128 #define NAND_EVTER_STAT_FTOER U(0x08000000)
129 #define NAND_EVTER_STAT_WPER U(0x04000000)
130 #define NAND_EVTER_STAT_ECCER U(0x02000000)
131 #define NAND_EVTER_STAT_DQSER U(0x01000000)
132 #define NAND_EVTER_STAT_RCW_DN U(0x00008000)
133 #define NAND_EVTER_STAT_BOOT_DN U(0x00004000)
134 #define NAND_EVTER_STAT_RCW_DN U(0x00008000)
135 #define NAND_EVTER_STAT_OPC_DN U(0x80000000)
136 #define NAND_EVTER_STAT_BBI_SRCH_SEL U(0x00000800)
137 #define NCFGR_BOOT U(0x80000000)
138 #define NAND_AUTOBOOT_TRGR_RCW_LD U(0x80000000)
139 #define NAND_AUTOBOOT_TRGR_BOOT_LD U(0x20000000)
142 #define NAND_RCW_LD U(0x80000000)
143 #define NAND_BOOT_LD U(0x20000000)
159 #define EMPTY_VAL_CHECK U(0xFFFFFFFF)
178 #define RCW_SRC_NAND_PORT_MASK U(0x00000080)
180 #define NAND_DEFAULT_CSPR U(0x00000053)
181 #define NAND_DEFAULT_CSOR U(0x0180C00C)
182 #define NAND_DEFAULT_EXT_CSPR U(0x00000000)
183 #define NAND_DEFAULT_EXT_CSOR U(0x00000000)
184 #define NAND_DEFAULT_FTIM0 U(0x181c0c10)
185 #define NAND_DEFAULT_FTIM1 U(0x5454141e)
186 #define NAND_DEFAULT_FTIM2 U(0x03808034)
187 #define NAND_DEFAULT_FTIM3 U(0x2c000000)
189 #define NAND_CSOR_ECC_MODE_DISABLE U(0x00000000)
190 #define NAND_CSOR_ECC_MODE0 U(0x84000000)
191 #define NAND_CSOR_ECC_MODE1 U(0x94000000)
192 #define NAND_CSOR_ECC_MODE2 U(0xa4000000)
193 #define NAND_CSOR_ECC_MODE3 U(0xb4000000)
206 #define RCW_SRC_NAND_BBI_MASK U(0x00000008)
207 #define RCW_SRC_NAND_BBI_MASK_NAND_2K U(0x00000002)
211 #define RCW_SRC_NAND_PAGE_MASK U(0x00000070)
212 #define RCW_SRC_NAND_PAGE_MASK_NAND_2K U(0x0000000C)
225 #define RCW_SRC_NAND_ECC_MASK U(0x00000007)
226 #define RCW_SRC_NAND_ECC_MASK_NAND_2K U(0x00000001)
233 #define NAND_SPARE_2K U(0x00000040)
234 #define NAND_SPARE_4K_ECC_M0 U(0x00000080)
235 #define NAND_SPARE_4K_ECC_M1 U(0x000000D2)
236 #define NAND_SPARE_4K_ECC_M2 U(0x000000B0)
237 #define NAND_SPARE_4K_ECC_M3 U(0x00000120)
238 #define NAND_SPARE_8K_ECC_M0 U(0x00000088)
239 #define NAND_SPARE_8K_ECC_M1 U(0x00000108)
240 #define NAND_SPARE_8K_ECC_M2 U(0x00000158)
241 #define NAND_SPARE_8K_ECC_M3 U(0x00000238)
242 #define NAND_SPARE_16K_ECC_M0 U(0x00000108)
243 #define NAND_SPARE_16K_ECC_M1 U(0x00000208)
244 #define NAND_SPARE_16K_ECC_M2 U(0x000002A8)
245 #define NAND_SPARE_16K_ECC_M3 U(0x00000468)