Lines Matching refs:U
16 #define BL31_SIZE U(0x40000)
21 #define PSTATE_ID_CORE_POWERDN U(7)
22 #define PSTATE_ID_CLUSTER_IDLE U(16)
23 #define PSTATE_ID_SOC_POWERDN U(27)
37 #define PLAT_MAX_RET_STATE U(1)
38 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
49 #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400)
59 #define TEGRA_IRAM_BASE U(0x40000000)
60 #define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */
61 #define TEGRA_IRAM_SIZE U(40000) /* 256KB */
66 #define TEGRA_GICD_BASE U(0x50041000)
67 #define TEGRA_GICC_BASE U(0x50042000)
72 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28)
77 #define TEGRA_MSELECT_BASE U(0x50060000)
79 #define MSELECT_CONFIG U(0x0)
80 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
81 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
82 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
83 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
84 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
108 #define TEGRA_TMRUS_BASE U(0x60005010)
109 #define TEGRA_TMRUS_SIZE U(0x1000)
114 #define TEGRA_CAR_RESET_BASE U(0x60006000)
115 #define TEGRA_BOND_OUT_H U(0x74)
116 #define APB_DMA_LOCK_BIT (U(1) << 2)
117 #define AHB_DMA_LOCK_BIT (U(1) << 1)
118 #define TEGRA_BOND_OUT_U U(0x78)
119 #define IRAM_D_LOCK_BIT (U(1) << 23)
120 #define IRAM_C_LOCK_BIT (U(1) << 22)
121 #define IRAM_B_LOCK_BIT (U(1) << 21)
122 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
123 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
124 #define GPU_RESET_BIT (U(1) << 24)
125 #define GPU_SET_BIT (U(1) << 24)
126 #define TEGRA_RST_DEV_SET_Y U(0x2a8)
127 #define NVENC_RESET_BIT (U(1) << 27)
128 #define TSECB_RESET_BIT (U(1) << 14)
129 #define APE_RESET_BIT (U(1) << 6)
130 #define NVJPG_RESET_BIT (U(1) << 3)
131 #define NVDEC_RESET_BIT (U(1) << 2)
132 #define TEGRA_RST_DEV_SET_L U(0x300)
133 #define HOST1X_RESET_BIT (U(1) << 28)
134 #define ISP_RESET_BIT (U(1) << 23)
135 #define USBD_RESET_BIT (U(1) << 22)
136 #define VI_RESET_BIT (U(1) << 20)
137 #define SDMMC4_RESET_BIT (U(1) << 15)
138 #define SDMMC1_RESET_BIT (U(1) << 14)
139 #define SDMMC2_RESET_BIT (U(1) << 9)
140 #define TEGRA_RST_DEV_SET_H U(0x308)
141 #define USB2_RESET_BIT (U(1) << 26)
142 #define APBDMA_RESET_BIT (U(1) << 2)
143 #define AHBDMA_RESET_BIT (U(1) << 1)
144 #define TEGRA_RST_DEV_SET_U U(0x310)
145 #define XUSB_DEV_RESET_BIT (U(1) << 31)
146 #define XUSB_HOST_RESET_BIT (U(1) << 25)
147 #define TSEC_RESET_BIT (U(1) << 19)
148 #define PCIE_RESET_BIT (U(1) << 6)
149 #define SDMMC3_RESET_BIT (U(1) << 5)
150 #define TEGRA_RST_DEVICES_V U(0x358)
151 #define TEGRA_RST_DEVICES_W U(0x35C)
152 #define ENTROPY_CLK_ENB_BIT (U(1) << 21)
153 #define TEGRA_CLK_OUT_ENB_V U(0x360)
154 #define SE_CLK_ENB_BIT (U(1) << 31)
155 #define TEGRA_CLK_OUT_ENB_W U(0x364)
156 #define ENTROPY_RESET_BIT (U(1) << 21)
157 #define TEGRA_CLK_RST_CTL_CLK_SRC_SE U(0x42C)
158 #define SE_CLK_SRC_MASK (U(7) << 29)
159 #define SE_CLK_SRC_CLK_M (U(6) << 29)
160 #define TEGRA_RST_DEV_SET_V U(0x430)
161 #define SE_RESET_BIT (U(1) << 31)
162 #define HDA_RESET_BIT (U(1) << 29)
163 #define SATA_RESET_BIT (U(1) << 28)
164 #define TEGRA_RST_DEV_CLR_V U(0x434)
165 #define TEGRA_CLK_ENB_V U(0x440)
170 #define TEGRA_FLOWCTRL_BASE U(0x60007000)
180 #define TEGRA_SB_BASE U(0x6000C200)
185 #define TEGRA_EVP_BASE U(0x6000F000)
190 #define TEGRA_MISC_BASE U(0x70000000)
191 #define HARDWARE_REVISION_OFFSET U(0x804)
192 #define APB_SLAVE_SECURITY_ENABLE U(0xC00)
193 #define PMC_SECURITY_EN_BIT (U(1) << 13)
194 #define PINMUX_AUX_DVFS_PWM U(0x3184)
195 #define PINMUX_PWM_TRISTATE (U(1) << 4)
200 #define TEGRA_UARTA_BASE U(0x70006000)
201 #define TEGRA_UARTB_BASE U(0x70006040)
202 #define TEGRA_UARTC_BASE U(0x70006200)
203 #define TEGRA_UARTD_BASE U(0x70006300)
204 #define TEGRA_UARTE_BASE U(0x70006400)
219 #define TEGRA_PMC_BASE U(0x7000E400)
220 #define TEGRA_PMC_SIZE U(0xC00) /* 3k */
234 #define TEGRA_MC_BASE U(0x70019000)
240 #define MC_SECURITY_CFG0_0 U(0x70)
241 #define MC_SECURITY_CFG1_0 U(0x74)
242 #define MC_SECURITY_CFG3_0 U(0x9BC)
245 #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
246 #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
247 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
248 #define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
249 #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
258 #define TEGRA_CL_DVFS_BASE U(0x70110000)
259 #define DVFS_DFLL_CTRL U(0x00)
260 #define ENABLE_OPEN_LOOP U(1)
261 #define ENABLE_CLOSED_LOOP U(2)
262 #define DVFS_DFLL_OUTPUT_CFG U(0x20)
263 #define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30)
264 #define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6)
269 #define TEGRA_SE1_BASE U(0x70012000)
270 #define TEGRA_SE2_BASE U(0x70412000)
271 #define TEGRA_PKA1_BASE U(0x70420000)
272 #define TEGRA_SE2_RANGE_SIZE U(0x2000)
273 #define SE_TZRAM_SECURITY U(0x4)
278 #define TEGRA_TZRAM_BASE U(0x7C010000)
279 #define TEGRA_TZRAM_SIZE U(0x10000)
284 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000)
285 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000)