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Searched refs:DEVICE1_BASE (Results 1 – 24 of 24) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8ulp/include/
H A Dplatform_def.h58 #define DEVICE1_BASE U(0x30000000) macro
115 #define DEVICE1_MAP MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW)
/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_def.h61 #define DEVICE1_BASE BASE_GICD_BASE macro
72 #define DEVICE1_BASE BASE_IWB_BASE macro
H A Dfvp_common.c69 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h67 #define DEVICE1_BASE (0x80000000) macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h67 #define DEVICE1_BASE (0x80000000) macro
/rk3399_ARM-atf/plat/xilinx/versal/aarch64/
H A Dversal_common.c29 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
/rk3399_ARM-atf/include/plat/nuvoton/npcm845x/
H A Dplatform_def.h147 #define DEVICE1_BASE BASE_GICD_BASE macro
164 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h83 #define DEVICE1_BASE (0x80000000) macro
/rk3399_ARM-atf/plat/xilinx/versal/include/
H A Dversal_def.h54 #define DEVICE1_BASE U(0xF9000000) macro
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_common.c30 #ifdef DEVICE1_BASE
31 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
H A Dqemu_spm.c18 #define MAP_DEVICE1_EL0 MAP_REGION_FLAT(DEVICE1_BASE, \
/rk3399_ARM-atf/plat/amd/versal2/aarch64/
H A Dcommon.c30 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
/rk3399_ARM-atf/plat/xilinx/versal_net/aarch64/
H A Dversal_net_common.c33 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c38 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
H A Dbl31_plat_setup.c142 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c42 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
H A Dbl31_plat_setup.c217 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
/rk3399_ARM-atf/plat/intel/soc/n5x/
H A Dbl31_plat_setup.c135 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
/rk3399_ARM-atf/plat/xilinx/versal_net/include/
H A Dversal_net_def.h108 #define DEVICE1_BASE U(0xE2000000) /* gic */ macro
/rk3399_ARM-atf/plat/amd/versal2/include/
H A Ddef.h113 #define DEVICE1_BASE U(0xE2000000) /* gic */ macro
/rk3399_ARM-atf/plat/xilinx/zynqmp/aarch64/
H A Dzynqmp_common.c34 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
/rk3399_ARM-atf/plat/qemu/qemu/include/
H A Dplatform_def.h234 #define DEVICE1_BASE 0x09000000 macro
/rk3399_ARM-atf/plat/qemu/qemu_sbsa/include/
H A Dplatform_def.h258 #define DEVICE1_BASE 0x60000000 macro
/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A Dzynqmp_def.h47 #define DEVICE1_BASE U(0xF9000000) macro